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Figure 2.3 The ultimate microprocessor development system. The processor accepts binary files through the brain waves in a configurable format!
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independently. The hardware development can go on in parallel, and you enter a phase that could be termed as test-and-debug phase. This is an iterative phase that continues till all your subroutines and hardware work as required. To complete this phase, you must take the help of as much test equipment and development tools (such as a programmer and an emulator) as possible to minimize the number of iterations. A realistic development system is illustrated in Figure 2.4. 9. Finally, you must integrate all the software and the hardware and test again. You again enter the test-and-debug phase till everything works as required. 10. During the writing of the software and building the hardware, an important activity that should not be missed is documentation. Documenting the design is extremely important not only for maintaining a record of your work, but also for testing during device lifetime and future revisions. 11. The final stage involves deploying the system in the target environment or the appropriate production line.
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THE AVR RISC MICROCONTROLLER ARCHITECTURE
3.1 Introduction
his chapter describes the AVR processor family in detail, covering the architectural aspects and the integrated peripheral components that are bundled with the CPU. The AVR is a RISC processor with a Harvard architecture. The Harvard architecture refers to the fact that the CPU has a program memory and a separate data memory. The AVR processor family has the following features:
1. On-chip and In System Programmable Flash memory used as Program Memory. All
the processors have on-chip flash program memory. This means you don t have to have external EPROMs or ROMs containing your program code. Also, the program memory can be programmed while the processor is in the target without removing it. This allows faster and easier system software upgrades. The program memory can be programmed in situ (i.e., without removing from the target system). The program memory can be programmed in two modes: serial and parallel, which we will discuss later. 2. 32-X-8 general-purpose working registers (in the true RISC tradition). A large register set means that variables can be stored inside the CPU rather than storing the variables in memory, as accessing memory, is time expensive. Thus the program will run faster.
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22 THE AVR MICROCONTROLLER ARCHITECTURE
3. On-chip data memory EEPROM and RAM in most devices. The CPU is Harvard
5. 6. 7. 8.
9. 10. 11.
architecture, and the EEPROM and the RAM is seen as DATA memory for storing constants and variables. 0 to 10-MHz clock speed operation. Most instructions operate in 1 clock cycle, and this leads to an almost 10-times performance improvement over conventional processors (e.g., the 8051) operating at equal clock frequency. Power On RESET circuit. On-chip programmable timer with separate prescalar. This is used for timing applications. Internal and external interrupt sources. Programmable watchdog timer with independent oscillator. This is used to recover in case of software crash but can also be used for other interesting applications as discussed in one of the project chapters. SLEEP and POWER DOWN modes of operation. This saves power when the processor is idling. Many chips with on-chip RC clock oscillator. Using the on-chip RC oscillator feature when available leads to an even lower component count. Wide device range (from a small 8-pin processor to a 68 pin processor), and one can choose a processor to suit a given requirement while being able to use the same development facilities. (Figure 3.1)
3.2 AVR Family Architecture
The AVR uses Harvard architecture. This entails separate data and program memory buses. Figure 3.2 illustrates the controller layout. The data memory data bus is an 8-bit bus and connects most of the peripheral components to the register file. The program memory data
FIGURE 3.1 Some AVR controllers.
AVR FAMILY ARCHITECTURE 23
bus is 16 bits wide and only feeds the instruction register. Even though Figure 3.2 refers to the AVR AT90S2313 controller, it applies equally well to all the processors and differs only to the extent of having additional (or less) peripheral components as well as differing in amounts of program memory and data memory. The program memory is a continuous chunk of flash memory. The exact amount varies from processor to processor. The AT90S1200, the base level processor, has 1 Kbyte of program memory organized as 512-X-16 bits, while the Mega103 has 128 Kbytes of memory organized as 64K-X-16 bits. A K here equals 1024 and not 1000. The program memory is accessed every clock cycle, and an instruction is loaded into the instruction register. The instruction register feeds the register file, selecting which of the registers will be used by the ALU for instruction execution. The instruction register output is also decoded by the instruction decoder to decide which control signals will be activated for completing the current instruction. The program memory, besides storing instructions, also stores interrupt vectors starting at address $0000. The actual program should start at memory location beyond the space meant for the vectors. The number of vectors vary from processor to processor.
Data Bus 8-bit 1K x 16 Program Flash Program Counter Status and Test Control Register Interrupt Unit SPI Unit Serial UART 8-bit Timer/Counter 16-bit Timer/Counter with PWM Watchdog Timer 128 x 8 EEPROM Analog Comparator 15 I/O Lines
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