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FIGURE 3.2 AVR processor architecture.
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24 THE AVR MICROCONTROLLER ARCHITECTURE
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AT90S1200 has 3 vectors and AT90S8515 has 13 vectors. Table 3.1 illustrates the complete vector space for AT90S8515. The data memory, on the other hand, is split up in different types. Figure 3.3 has the various memory maps available to an AVR processor. The data memory has in all five different components:
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1. A register file with 32 registers of 8-bit width. All processors of the AVR family have
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this register file.
2. 64 I/O registers of 8 bits each. All the processors do not have all the 64 registers. Some
have more than others, depending on the number of peripheral components on the chip. These registers are really part of on-chip SRAM and can be accessed either as SRAM with addresses between $20 and $5F or as I/O registers with addresses between $00 and $3F. Most often, all of these registers are accessed as I/O registers rather than as SRAM. 3. Internal SRAM. This is available on most of the AVR processors except the baseline processors such as the AT90S1200. The amount of SRAM varies between 128 bytes to 4 Kbytes. The SRAM is used for stack as well as storing variables. During interrupts and subroutine calls, the current program counter value is stored on the stack. The size of the stack is limited by the available on-chip SRAM. The current stack location is indicated by the stack pointer. The stack pointer is 1 byte on smaller processors such as AT90S2313 and is 2 bytes on larger processors such as the AT90S8515. The stack pointer must be initialized after reset and before the stack can be used. For those processors that do not have on-chip SRAM such as the AT90S1200, a hardware stack is available to store program return addresses. This hardware stack can only store up to 3 return addresses.
TABLE 3-1 PROGRAM MEMORY VECTOR SPACE FOR AT90S8515 VECTOR COMMENTS
PROGRAM MEMORY ADDRESS
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C
Reset EXT_INT0 EXT_INT1 TIM_CAPT TIM1_COMA TIM1_COMB TIM1_OVF TIM0_OVF SPI_STC UART_RXC UART_DRE UART_TXC ANA_COMP
Reset handler IRQ0 handler IRQ1 handler Timer1 capture handler Timer1 compareA handler Timer1 compareB handler Timer1 overflow handler Timer0 overflow handler SPI transfer complete handler UART RX complete handler UART UDR empty handler UAT TXC complete handler Analog comparator handler
THE REGISTER FILE 25
Program Memory
Data Memory 0000 32 Register $1F File
Data EEPROM 0000
I/O Registers Internal SRAM
16 bits
$5F $60
8 bits
End Address
External SRAM 8 bits
End Address End Address
FIGURE 3.3 AVR processor memory map. 4. External SRAM. This is possible only on the larger processors of the AVR family.
Those processors that have external data and memory access ports (such as the AT90S8515) can use any available external SRAM the user may decide to implement. 5. EEPROM. The EEPROM is available on almost all AVR processors and is accessed in a separate memory map. The starting address of the EEPROM is always $0000. Various processors have between 64 bytes and 4 Kbytes of EEPROM. The EEPROM can be read and written by any program. Reading the EEPROM is faster than writing the EEROM. The EEPROM can be written to about 100,000 times. Most of the AVR instructions are 1 word (2 bytes) long and so take 1 program memory location. Many instructions execute in a single clock cycle, and a few take 2 or more clock cycles. This single-cycle execution is achieved due to the use of a 2-stage pipeline. The pipeline works by concurrently acquiring a new instruction from the program memory while the previous instruction is executing in the other part of the processor. Thus instruction fetch and decode and execution are processes that are being performed by the processor concurrently. Now let us look at the various components that make the AVR processor.
3.3 The Register File
All AVR processors have 32 general-purpose registers. Some of these registers have additional special functions. The registers are named R0 through R31. The register file is broken up into 2 parts with 16 registers each, R0 to R15 and R16 to R31. All instructions that
26 THE AVR MICROCONTROLLER ARCHITECTURE
operate on the registers have direct access and single-cycle access to all the registers. The exception is the SBCI, SUBI, CPI, ANDI, and ORI instructions as well as the LDI instruction. These instructions operate only on registers R16 to R31. Registers R0 and R26 through R31 have additional functions. R0 is used in the instruction LPM (load program memory), while R26 through R31 are used as pointer registers as illustrated in Figure 3.4. These pointer registers are used in many of the register indirect instructions.
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