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3.4 The ALU
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The arithmetic logic unit (ALU) performs such operations as bit, arithmetic, and logic upon the contents of the registers and writes back the result into the register file into the designated register. These operations are performed in a single clock cycle. Each ALU operation affects the flags in the STATUS register, depending upon the instruction.
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Address $00 $01 $02 R0 R1 R2 R3
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R14 $0F $10 $11 R15 R16 R17
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R26 R27 R28 R29 $1E $1f R30 R31
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X-Register Low Byte X-Register High Byte Y-Register Low Byte Y-Register High Byte Z-Register Low Byte Z-Register High Byte
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FIGURE 3.4 AVR register file.
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3.5 Memory Access and Instruction Execution
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The AVR processor is driven by the system clock, which can be sourced from outside or, if available and enabled, an internal RC clock can be used. This system clock without any division is used directly for all accesses inside the processor. The processor has a two-stage pipeline, and instruction fetch/decode is performed concurrently with the instruction execution. This is illustrated in Figure 3.5. Once the instruction is fetched, if it is an ALU-related instruction, it can be executed by the ALU as illustrated in Figure 3.6 in a single cycle. On the other hand, the SRAM memory access takes two cycles, as illustrated in Figure 3.7. This is because the SRAM access uses a pointer register for the SRAM address. The pointer register is one of the pointer registers (X, Y, or Z register pairs). The first clock cycle is needed to access the register file and to operate upon the pointer register (the SRAM access instructions allow pre/post-address increment operation on the pointer register). At the end of the first clock cycle, the ALU performs this calculation, and then this address is used to access the SRAM location and to write into it (or read from it into the destination register), as illustrated in Figure 3.7.
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3.6 I/O Memory
The I/O memory is the gateway to all the peripheral components of the AVR processor. It is implemented as SRAM and can be accessed in two ways: as SRAM as well as I/O registers. As SRAM, the addresses are beyond $20 to $5F and as I/O registers, the addresses start at $00 to $3F. We will look at the I/O registers as registers rather than as SRAM. We will look at most I/O registers and the function of these registers. However, for a specific chip, it is advisable to refer to individual data sheets for up-to-date and accurate information. The discussion here refers to most common registers and their functions. An important point to note here is regarding accessing the various I/O registers. To access the I/O registers, the AVR offers IN and OUT instructions. These instructions can
FIGURE 3.5 Instruction fetch/decode and instruction execution.
FIGURE 3.6 ALU execution consisting of register fetch, execute, and write back.
FIGURE 3.7 On-chip SRAM data access cycles.
access all the I/O registers from $00 to $3F. Besides IN and OUT, the AVR also supports bit addressing on some of the registers, namely from $00 to $1F. With the help of the bit instructions SBI and CBI, any bit in any of the registers ($00 to $1F) can be set on reset. This is a time-saving method compared to reading the register, changing the bit, and writing the value back to the register. For the rest of the registers, one has to use the other method, which takes about three times more clock cycles.
The STATUS register contains 8-flag bits that indicate the current state of the processor. All these bits are cleared (i.e., at logic 0 ) at reset and can be read or written to by the program. The I/O address of the STATUS register is $3F (memory address is $5F). (Figure 3.8) The various flags of the STATUS register and their functions are:
1. Bit7-I: Global Interrupt Enable. Setting this bit enables all the interrupts. Resetting this
disables all interrupts.
2. Bit6-T: Bit Copy Storage. Used with BLD (bit load) and BST (bit store) instruction for
loading and storing bits from one register to another.
7 I/O Address = $3F Initial Value I 0
6 T 0
5 H 0
4 S 0
3 V 0
2 N 0
1 Z 0
0 C 0
FIGURE 3.8 The processor STATUS register. 3. Bit5:H. Half Carry Flag. Indicates half carry in some arithmetic instructions. 4. Bit4:S. Sign Flag. This bit is the exclusive OR between the negative flag N and the 5. 6. 7. 8.
Overflow flag V . Bit3:V Two s Complement Overflow Flag. . Bit2:N. Negative Flag. Bit1:Z. Zero Flag. Indicates a zero result after an arithmetic or logical operation. Bit0:C. Carry Flag. Indicates a carry in arithmetic or logical operation.
The STATUS register is not stored by the machine during an interrupt operation. The instruction in an interrupt routine can modify the STATUS flag bits, and so the user program must store and retrieve the STATUS register during an interrupt.
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