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SP: STACK POINTER REGISTER
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This register is 1 byte wide for processors that have up to 256 bytes of SRAM and is 2 bytes wide (called SPH and SPL) for those processors that have more than 256 bytes of SRAM. This register is used to point to the area in SRAM that is the top of the stack. The stack is used to store return addresses by the processor during an interrupt and subroutine call. Since the SP is initialized to $00 (or $0000 for a 2-byte SP) at reset, the user program must initialize the SP appropriately, as the SRAM starting address is not $00. SRAM starting address is $60. The stack grows down in memory address i.e., pushing a value on stack results in the SP getting decremented. Popping a value out of stack increments the SP.
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GIMSK: GENERAL INTERRUPT MASK REGISTER
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The GIMSK register is used to enable and disable individual external interrupts by setting and resetting the concerned bit respectively. However, the interrupt to be actually serviced, the I bit in the STATUS register (SREG), must also be set to 1. (Figure 3.9.)
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GIFR: GENERAL INTERRUPT FLAG REGISTER
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The bits in GIFR indicate if an interrupt has occurred. If an external interrupt occurs, the corresponding INT flag in GIFR is set to 1. If the interrupt gets serviced (which happens if the I bit and the corresponding INT bit in GIMSK register is 1 ), then the flag is reset. The flag can also be reset by writing a logical 1 to it. (Figure 3.10.)
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7 I/O Address = $3B Initial Value INT1 0
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FIGURE 3.9 The general interrupt mask register.
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7 I/O Address = $3A Initial Value
INTF1 INTF0 0 0 0 0 0 0 0 0
FIGURE 3.10 The general interrupt flag register.
MCUCR: MCU GENERAL CONTROL REGISTER
The bits in MCUCR allow general processor control. This includes external SRAM access enable/disable, sleep mode, and external interrupt sense control. (Figure 3.11.)
1. Bit7:SRE. External SRAM Enable. Setting this bit to 1 allows external SRAM
4. 5. 6.
access on processors that have the capability. PortA becomes AD0-7, PortC becomes A8-15, and WR* and RD* signals are activated on PortD as alternate pin functions. When this bit is 0, the ports function as normal ports and external SRAM access is disabled. Bit6:SRW. External SRAM Access Wait State Bit. When this bit is 1, an extra wait state is inserted in the SRAM access cycle. Thus the SRAM is accessed in 4 cycles. When this bit is 0, the SRAM is accessed in 3 cycles. Bit5:SE. Sleep Enable. Setting this bit to 1 enables the processor to go in one of the sleep modes. After setting this bit to 1, the program must execute the SLEEP instruction. Bit4:SM. Sleep Mode. A 1 in this bit puts the processor in idle mode. A 0 means power down mode. Bit3, 2:ISC11, ISC10. Interrupt sense control bit for INT1 as per Table 3.2. Bit1, 0:ISC01, ISC00. Interrupt sense control bit for INT0 as per Table 3.3.
MCUSR: MCU STATUS REGISTER
The MCU status register provides information about the source of reset. (Figure 3.12.) The MCUSR contains 2 bits which indicate the source for the reset as per Table 3.4.
I/O MEMORY 31
7 I/O Address = $35 Initial Value SRE 0
6 SRW 0
5 SE 0
4 SM 0
3 ISC11 0
2 ISC10 0
1 ISC01 0
0 ISC00 0
FIGURE 3.11 The MCU general control register.
TABLE 3-2 ISC11
INTERRUPT1 SENSE CONTROL ISC10 DESCRIPTION
0 0 1 1
0 1 0 1
Low level on INT1 generates interrupt Reserved Falling edge on INT1 generates interrupt Rising edge on INT1 generates interrupt
TABLE 3-3 ISC01
INTERRUPT0 SENSE CONTROL ISC00 DESCRIPTION
0 0 1 1
0 1 0 1
Low level on INT0 pin generates interrupt Reserved Falling edge on INT0 pin generates interrupt Rising edge on INT0 pin generates interrupt
5 4 3 2 1 EXTRF 0 PORF 0
I/O Address = $34 Initial Value 0 0 0 0 0 0
FIGURE 3.12 The MCU status register.
TCCR0: TIMER/COUNTER0 CONTROL REGISTER
The Timer/Counter0 Control register is used to control the operation of the processor Timer/Counter0. This is a simple timer that counts up from the loaded count. The count is incremented at each clock signal at its input. The clock signal can be selected from one of seven sources as illustrated in Table 3.5. The eighth option allows the counter/timer to be stopped.
TCNT0: TIMER/COUNTER0 REGISTER
This is the actual timer/counter register. A value loaded in this register is used as the starting value, and the timer increments this value at each of its clock signals if the
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