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32 THE AVR MICROCONTROLLER ARCHITECTURE
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TABLE 3-4 PORF AND EXTRF VALUES AFTER RESET. X MEANS UNDEFINED AND Y MEANS UNCHANGED EXTRF PORF DESCRIPTION
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CLOCK0 PRESCALE SELECTION CS01 CS00 DESCRIPTION
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Stop the timer/counter0 CK CK/8 CK/64 CK/256 CK/1024 External pin T0, falling edge External pin T0, rising edge
counter/timer is enabled through the TCCR0 register. After the Timer/Counter0 overflows, it resets to $00 and continues counting up for each Timer/Counter0 clock signal. (Figures 3.13 and 3.14.)
TCCR1A: TIMER/COUNTER1 CONTROL REGISTER A
TCCR1A is a control register for Timer/Counter1. The signals for this registers are:
1. Bits 7,6:COM1A1, COM1A0: Compare Output Mode1, bits 1 and 0. The COM1A1
and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1-Output Compare pin1. This is an alternative function to the I/O port, and the corresponding direction control bit must be set to 1 to control an output pin. For devices with 2 compare functions, bits 5 and 4 of the control register have similar functions to bits 7 and 6. The control configuration is illustrated in Table 3.6. 2. Bits 1,0-PWM11, PWM10: Pulse Width Modulator Select Bits. These bits select PWM operation of Timer/Counter1 as specified in Table 3.7. (Also see Figure 3.15.)
I/O MEMORY 33
7 I/O Address = $33 Initial Value 0
2 CS02
1 CS01 0
0 CS00 0
FIGURE 3.13 The Timer/Counter0 control register.
7 I/O Address = $32 Initial Value MSB 0
0 LSB
FIGURE 3.14 The Timer/Counter0 register.
TABLE 3-6 COM1X1 COMPARE1 MODE SELECT. X IS A OR B COM1X0 DESCRIPTION
0 0 1 1
0 1 0 0
Timer/counter1 disconnected from output pin OC1X. Toggle OC1X output. Clear OC1X output to 0. Set OC1X output to 1.
TABLE 3-7 PWM11
PWM MODE SELECT PWM10 DESCRIPTION
0 0 1 1
0 1 0 0
PWM operation of timer/counter1 is disabled. 8-bit PWM. 9-bit PWM. 10-bit PWM.
TCCR1B: TIMER/COUNTER1 CONTROL REGISTER B
The bits of the TCCR1B register have the following:
1. Bit7:ICNC1:Input Capture1 Noise Canceler (4 CKs). When the ICNC1 bit is cleared to
0, the input capture trigger noise canceler function is disabled. The input capture is
34 THE AVR MICROCONTROLLER ARCHITECTURE
7 I/O Address = $2F Initial Value
5 COM1B1 0
4 COM1B0 0
1 PWM11
0 PWM10 0
COM1A1 COM1A0 0 0
FIGURE 3.15 The Timer/Counter1 control RegisterA.
triggered at the first rising/falling edge sampled on the ICP input capture pin as specified. When the ICNC1 bit is set to 1, four successive samples are measures on the ICP, input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is the XTAL clock frequency. 2. Bit6:ICES1:Input Capture1 Edge Select. While the ICES1 bit is cleared to 0, the Timer/Counter1 contents are transferred to the Input Capture Register, ICR1, on the falling edge of the input capture pin, ICP. While the ICES1 bit is set to 1, the Timer/Counter1 contents are transferred to the Input Capture Register, ICR1, on the rising edge of the input capture pin, ICP. 3. Bit3:CTC1:Clear Timer/Counter1 on Compare Match. When the CTC1 control bit is set to 1, the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the compare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used, and the compareA register is set to C, the timer will count as follows if CTC1 is set:
... C-2 C-1 C 0 1 ...
When the prescaler is set to divide by 8, the timer will count like this:
... C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 C, 0, 0, 0, 0, 0, 0, 0 ...
In PWM mode, this bit has no effect. 4. Bits 2,1,0-CS12, CS11, CS10:Clock Select1, bit 2,1 and 0. The ClockSelect1 bits 2,1 and 0 define the prescaling source of Timer/Counter1 similar to Timer/Counter0. (See Figure 3.16.)
TCNT1H, TCNT1L: TIMER/COUNTER1
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled. (Figure 3.17.) TCNT1 Timer/Counter1 Write: When the CPU writes to the high-byte TCNT1H, the written data is placed in the TEMP register. Next, when the CPU writes the low-byte TCNT1L, this byte of data is combined with the byte data in the TEMP register, and all 16 bits are written to the TCNT1 Timer/Counter1 register simultaneously. Consequently, the high-byte TCNT1H must be accessed first for a full 16-bit register write operation.
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