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7 I/O Address = $2E Initial Value ICNC1 0
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FIGURE 3.16 The Timer/Counter1 control RegisterB.
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15 I/O Address = $2D Initial Value MSB 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 TCNT1H
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0 LSB TCNT1L
FIGURE 3.17 The Timer/Counter1 register.
TCNT1 Timer/Counter1 Read: When the CPU reads the low-byte TCNT1L, the data of the low-byte TCNT1L is sent to the CPU and the data of the high-byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high-byte TCNT1H, the CPU receives the data in the TEMP register. Consequently, the low-byte TCNT1L must be accessed first for a full 16-bit register read operation. The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value.
3.6.12 OCR1AH, OCR1AL: TIMER/COUNTER1 OUTPUT COMPARE REGISTERS
The output compare register is a 16-bit read/write register. The Timer/Counter1 Output Compare Register contains the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register. Since the Output Compare Register, OCR1A, is a 16-bit register, a temporary register TEMP is used when OCR1A is written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL, the TEMP register is simultaneously written to OCR1AH. Consequently, the high-byte OCR1AH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1 and ICR1. If the main program and interrupt routines also perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled.
36 THE AVR MICROCONTROLLER ARCHITECTURE
3.6.13 OCR1BH, OCR1BL: TIMER/COUNTER1 OUTPUT COMPARE REGISTERS
The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register. A compare match only occurs if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers OCR1A and OCR1B are 16bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1 and ICR1. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and from interrupt routines if interrupts are allowed from within interrupt routines.
15 I/O Address = $2B Initial Value MSB 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 OCR1AH
7 I/O Address = $2A Initial Value 0
0 LSB OCR1AL
FIGURE 3.18 The Timer/Counter1 output compare RegisterA.
15 I/O Address = $29 Initial Value MSB 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 OCR1BH
7 I/O Address = $28 Initial Value 0
0 LSB OCR1BL
FIGURE 3.19 The Timer/Counter1 output compare RegisterB.
I/O MEMORY 37
3.6.14 ICR1H, ICR1L: Timer/Counter1 Input Capture Registers
The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting, ICES1) of the signal at the input capture pin, ICP, is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register, ICR1. At the same time, the input capture flag, ICF1, is set to 1. Since the Input Capture Register, ICR1, is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low-byte ICR1L, the data is sent to the CPU and the data of the high-byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high-byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low-byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1 and OCR1A. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled. (Figure 3.20.)
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