barcode reader using c#.net WDTCR: WATCHDOG TIMER CONTROL REGISTER in Software

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WDTCR: WATCHDOG TIMER CONTROL REGISTER
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1. Bit4:WDTOE. Watchdog Turn Off Enable. This bit is used in conjunction with the
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WDE bit. This bit is set to 1, when WDE is cleared to 0 to disable the watchdog timer. The processor clears this bit after four clock cycles. 2. Bit3:WDE. Watchdog Enable. When set to 1, the watchdog timer is enabled. To disable the watchdog, this bit is cleared to 0 and the WDTOE is set to 1. To disable the watchdog timer, the following procedure is employed: In a single operation, set WDTOE and WDE to 1. Clear WDE to 0 within next 4 clock cycles. This will then disable the watchdog timer. 3. Bit2-0:WDP2, WDP1, WDP0. Watchdog Timer Prescaler. These bits are used as in Table 3.8 to select the watchdog timer timeouts. (See Figure 3.21.)
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EEAR: EEPROM ADDRESS REGISTER
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The EEPROM Address register is two bytes wide for processors with more than 256 bytes of EEPROM and one byte wide for the rest.
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15 I/O Address = $25 Initial Value MSB 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 ICR1H
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7 I/O Address = $24 Initial Value 0
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0 LSB ICR1L
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FIGURE 3.20 The Timer/Counter1 input capture register.
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TABLE 3-8 WDP2
WATCHDOG TIMER PRESCALE SELECT WDP1 WDP0 WDT CYCLES TYPICAL TIMEOUT AT 5 V
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
16 K 32 K 64 K 128 K 256 K 512 K 1024 K 2048 K
4 WDTOE 3 WDE 0
15 ms 30 ms 60 ms 120 ms 240 ms 490 ms 970 ms 1.9 s
2 WDP2 0 1 WDP1 0 0 WDP0 0
I/O Address = $21 Initial Value 0 0 0
FIGURE 3.21 The watchdog timer control register.
EEDR: EEPROM DATA REGISTER
The EEPROM DATA register is used to read and write data from/to the EEPROM. The EEPROM is 8 bits wide.
EECR: EEPROM CONTROL REGISTER
The EECR is used to control data read and write operations to the EEPROM. (Figure 3.22.)
1. Bit2:EEMWE:EEPROM Master Write Enable. Setting EEMWE to 1 and then set-
ting EEWE to 1 only will write data in the EEDR register to the EEPROM. If EEMWE is set to 1, the hardware clears this bit to 0 after 4 clock cycles. 2. Bit1:EEWE. EEPROM Write Enable. When set to 1 while EEMWE is also 1, the EEDR data is written to the EEPROM at the address specified by the EEPROM Address register. The EEWE bit remains 1 during the write cycle, which may take up to 2.5 ms at 5V After this time has elapsed, the EEWE is cleared by hardware to 0. . The sequence for writing data to the EEPROM is as follows: Wait till EEWE is cleared to 0. Write EEPROM address to EEAR. Write EEPROM data to EEDR. Set EEMWE to 1 and within four clock cycles set EEWE to 1. This will write the data in EEDR to the EEPROM location whose address is in EEAR.
3. Bit0:EERE:EEPROM Read Enable. To read EEPROM data, load EEAR with the cor-
rect address, set EERE to 1, and then clear EERE to 0. This will get the data in EEDR. Before starting a read cycle, the program would poll the EEWE flag till EEWE is 0 to ensure that the any write cycle is not in progress.
I/O MEMORY 39
7 I/O Address = $1C Initial Value 0
2 EEMWE
1 EEWE 0
0 EERE 0
FIGURE 3.22 The EEPROM control register.
PORTB: PORTB DATA REGISTER
PORTB register is a read/write register. It is initialized at reset to $00. When programmed as an output, then writing to PORTB will allow you to change the logic state at the PORTB pins.
DDRB: PORTB DATA DIRECTION REGISTER
This register is used to control the direction of each of the pins of the PORTB. Writing a 0 (which is also the reset value) in any bit of this register will make the corresponding POTB bit as input, and writing a 1 will make it an output bit.
PINB: INPUT PINS ON PORTB
This is a read-only port, and with this you can read the logic at the physical pin of PORTB. PINB is not a register, and reading PINB allows you to read the logical values on the pins of PORTB.
PORTD: PORTD DATA REGISTER
Same function as PORTB register.
DDRD: PORTD DATA DIRECTION REGISTER
Same function as DDRB register.
PIND: INPUT PINS ON PORTD
Same function as PINB port.
SPI I/O DATA REGISTER
This is the read/write register used for data transfer between the register file and the SPI shift register. Writing to this register initiates data transmission, and reading from it causes the shift register receive buffer to be read. More details in the SPI port section. (Figure 3.23.)
SPI STATUS REGISTER
1. Bit7:SPIF. SPI Interrupt Flag. When a SPI serial transfer is complete and the SPIE bit
in SPCR is set to 1 and the global interrupts are enabled, then the SPIF flag is set to 1. SPIF is cleared to 0 by the processor when the corresponding interrupt is executed. Alternatively, the SPIF bit is cleared by reading the SPI status register when SPIF is 1 and then accessing the SPI data register.
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