barcode reader using c#.net THE AVR MICROCONTROLLER ARCHITECTURE in Software

Printer ANSI/AIM Code 128 in Software THE AVR MICROCONTROLLER ARCHITECTURE

40 THE AVR MICROCONTROLLER ARCHITECTURE
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7 I/O Address = $0F Initial Value MSB 0
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0 LSB
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FIGURE 3.23 The SPI data register.
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7 I/O Address = $0E Initial Value SPIF 0 6 WCOL 0 0 0 0 0 0 0 5 4 3 2 1 0
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FIGURE 3.24 The SPI status register. 2. Bit6:WCOL. Write Collision Flag. This bit is set if the SPI Data Register (SPDR) is
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written during a data transfer. This bit is cleared, together with the SPIF, to 0 by first reading the SPI Status Register when WCOL is set to 1 and then accessing the SPI Data Register. (Figure 3.24.)
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SPI CONTROL REGISTER
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1. Bit7:SPIE. SPI Interrupt Enable. This bit causes an SPI interrupt to be generated if the
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SPIF bit in the SPSR register is set and the global interrupts are enabled.
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2. Bit6:SPE. SPI Enable. When this bit is set to 1, the SPI is enabled. 3. Bit5:DORD. Data Order. When set to 1, LSB of the data word is transmitted first.
When cleared to 0, the MSB of the data word is transmitted first.
4. Bit4:MSTR. Master/Slave Select. When set to 1, the SPI port is in master mode and
when cleared to 0, it is a slave port. If SS* is configured as input and is driven low, then the MSTR will be cleared to 0 and SPIF in SPSR will be set. The user will have to set MSTR to 1 again to start as master. 5. Bit3:CPOL. Clock Polarity. When set to 1, the SCK is high when idle and when cleared to 0, SCK is low when idle. 6. Bit2:CPHA. Clock Phase. Determines the active phase of the clock. 7. Bit1-0:SPR1, SPR0. SPI Clock Rate Select. These bits determine the SCK clock rate when configured as master, as per Table 3.9. If the device is a slave, these bits have no effect on the SCK frequency. (Figure 3.25.)
UART I/O DATA REGISTER
The UART Data I/O registers are actually two separate registers, sharing the same physical address. When data is written to this address, it gets written to the data transmit register, and when reading from this address it is read from the data receive register. (Figure 3.26.)
UART STATUS REGISTER
The UART status register is used to monitor the status of the UART. The significant bits of the USR are:
I/O MEMORY 41
TTABLE 3-9 SCK FREQUENCY. FCL IS THE PROCESSOR OSCILLATOR FREQUENCY SPR1 SPR0 SCK FREQUENCY
0 0 1 1
0 1 0 1
Fcl/4 Fcl/16 Fcl/64 Fcl/128
7 I/O Address = $0D Initial Value SPIE 0
6 SPE 0
5 DORD 0
4 MSTR 0
3 CPOL 0
2 CPHA 0
1 SPR1 0
0 SPR0 0
FIGURE 3.25 The SPI control register.
7 I/O Address = $0C Initial Value MSB 0 0 0 0 0 0 0 6 5 4 3 2 1 0 LSB 0
FIGURE 3.26 The UART I/O data register.
1. Bit7:RXC:UART Receive Complete. When this bit is set to 1, it indicates that the
4. 5.
UART has received a data byte from the receiver shift register. RXC is cleared by reading the UDR. Bit6:TXC:UART Transmit Complete. This bit is set to 1 when a complete data byte including the stop bit is shifted out from the transmit shift register and no new data is written to the UDR. TXC is cleared to 0 by hardware by executing the corresponding interrupt handler or by software by writing a 1 to the TXC bit. Bit5:UDRE:UART Data Register Empty. This bit is set to 1, when the data written to the UDR is transferred to the transmit shift register. This bit indicates that the UDR is ready to receive a new byte. Bit4:FE:Framing Error. This bit is set to 1, when the incoming stop bit is 0 (when it should be 1 ). The FE is cleared when the incoming stop bit is 1. Bit3:OR:Overrun Error. This bit is set to 1, when a valid data in the UDR is not read before a new data is shifted in the UDR from the UART receiver shift register. (Figure 3.27.)
UART CONTROL REGISTER
1. Bit7:RXCIE:RX Complete Interrupt Enable. This bit when set to 1 causes the
Receive Complete Interrupt when the RXC bit in the USR is set to 1 and the global interrupts are enabled.
42 THE AVR MICROCONTROLLER ARCHITECTURE
7 I/O Address = $0B Initial Value RXC 0
6 TXC 0
5 UDRE 1
4 FE 0
3 OR 0
FIGURE 3.27 The UART status register. 2. Bit6:TXCIE:TX Complete Interrupt Enable. This bit when set to 1 causes the
4. 5.
7. 8.
Transmit Complete Interrupt when the TXC bit in the USR is set to 1 and the global interrupts are enabled. Bit5:UDRIE:UART Data Register Empty Interrupt Enable. When this bit is set to 1 and the UDRE bit in the USR sets to 1, the UDRE data register empty interrupt will be executed provided the global interrupts are enabled. Bit4:RXEN:Receiver Enable. When this bit is set to 1, the UART receiver is enabled. Bit3:TXEN:Transmitter Enable. This bit when set to 1 enables the transmitter. When disabling the transmitter by writing a 0 to this bit, the transmitter is disabled but not before any character in the transmit shift register or the UDR transmit register is shifted out. Bit2:CHR9:9-bit Characters. When this bit is set to 1, the transmitted and received characters are 9 bits long besides the start and the stop bit. The 9th bit can be used as an extra stop bit or parity bit. Bit1:RXB8:Receive Data Bit 8. When CHR9 is set to 1, the RXB8 is the 9th bit of the received character. Bit0:TXB8:Transmit Data Bit 8. When CHR9 is set to 1, the TXB8 is the 9th data bit in the character to be transmitted. (Figure 3.28.)
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