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UART BAUD RATE REGISTER
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The baud rate generator for the UART is a frequency divider which provides the time ticks for the data transmission and reception according to the following equation: BaudRate = Fck/ (16 * (UBRR + 1) ) Fck is the system clock frequency. UBRR is the contents of the UART Baud Rate Register. (Figure 3.29.)
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3.6.32 ACSR: ANALOG COMPARATOR CONTROL AND STATUS REGISTER
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The ACSR is used to control the comparator operation as well as to monitor the comparator output.
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1. Bit7:ADC:Analog Comparator Disable. When set to 1, the power to the comparator
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is switched off.
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2. Bit5:ACO:Analog Comparator Output. This is the output of the comparator. 3. Bit4:ACI:Analog Comparator Interrupt Flag. This bit is set to 1 when a comparator
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event has triggered a comparator interrupt mode defined by ACIS1 and ACIS0. The
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THE EEPROM 43
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7 I/O Address = $0A Initial Value RXCIE 0
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6 TXCIE 0
5 UDRIE 0
4 RXEN 0
3 TXEN 0
2 CHR9 0
1 RXB8 1
0 TXB8 0
FIGURE 3.28 The UART control register.
7 I/O Address = $09 Initial Value MSB 0 0 0 0 0 0 0 6 5 4 3 2 1 0 LSB 0
FIGURE 3.29 The UART baud rate register.
comparator interrupt is executed if the ACIE bit is set to 1 and the global interrupts are enabled. 4. Bit3:ACIE:Analog Comparator Interrupt Enable. When set to 1, the analog comparator interrupt is enabled. When reset to 0, the comparator interrupt is disabled. 5. Bit2:ACIC:Analog Comparator Input Capture Enable. When set to 1, the comparator output is connected to the input capture front-end circuit of the Timer1. 6. Bit1,0:ACIS1, ACIS0:Analog Comparator Interrupt Mode Select. The combinations of these bits selects the interrupt modes as illustrated in Table 3.10. Also see Figure 3.30.
3.7 The EEPROM
All AVR controllers have on-chip EEPROM. The amount of EEPROM varies from 64 bytes on the AT90S1200, Tiny10/12 to 4Kbytes on the Mega103. The EEPROM is accessed through the EEPROM access registers, namely: EEPROM Address Register (EEAR), EEPROM Data Register (EEDR), and the EEPROM Control Register (EECR). For those devices with more than 256 bytes of EEPROM, the EEAR is actually two registers, EEARL and EEARH. The EEAR (either as a single register or as a double register) is used to set the address of the EEPROM to which data is to be written or from which the data is to be read. The EEAR is a read/write register, i.e., the register can be read to see what EEPROM address has been set. The EEDR is the EEPROM data register and is a read/write register. When you want to write data to the EEPROM, you load the required data into the EEDR. When you want to read data from the EEPROM, after the reading process is over, you read the EEDR for the data. The EECR has the necessary control bits for reading and writing the EEPROM. Writing to an EEPROM is not as simple as writing to SRAM, for example. The Write access time for the EEPROM on the AVR controllers is of the order or 2.5 to 4.0 ms, depending upon the supply voltage. The EEWE control bit in the EECR allows the user to detect when a previously requested data has been written to the EEPROM and whether a new byte can be written. The following piece of code illustrates how a byte of data can be read from the EEPROM.
44 THE AVR MICROCONTROLLER ARCHITECTURE
TABLE 3-10 ACIS1
ACIS1, ACIS0 SETTINGS ACIS0 INTERRUPT MODE
0 0 1 1
0 1 0 1
Interrupt on output toggle. Reserved. Interrupt on falling output edge. Interrupt on rising output edge.
5 ACO 0 0 4 ACI 0 3 ACIE 0 2 ACIC 0 1 ACIS1 0 0 ACIS0 0
I/O Address = $08 Initial Value
ACD 0
FIGURE 3.30 The analog comparator control and status register.
; -EEPROM Data eep_notrdy: sbic EECR,1 rjmp eep_notrdy read: out EEAR, ZL sbi EECR, 0 nop nop in read_reg, EEDR ; -EEPROM Data Read Start ;skip if EEWE clear ;Waits until EEPROM ready ;output address ;set EERE (Read-strobe) low ;mandatory 2 cycle delay ;inputs data Read End -
The following piece of code illustrates how a byte of data can be written to the EEPROM. To prevent any failure of data write to the EEPROM, it is important to ensure that the EEPROM write sequence of setting the EEWE bit and the EEMWE bit occurs without interruption; therefore global interrupts are disabled prior to the critical write sequence of setting the EEWE and the EEMWE bit, and after this the interrupts are enabled. However, this should only be done if interrupts are at all being used in the system. If the interrupts are not being used, there is no need to unnecessarily enable the interrupts.
; - - - - -EEPROM Data Write - - - - eep_notrdy: sbic EECR,1 ;skip if EEWE clear rjmp eep_notrdy ;Waits until EEPROM ready write: out EEAR, ZL ;output address out EEDR, write_data cli ;disable all interrupts sbi EECR, 1 ;set EEWE (Write-enable) sbi EECR, 2 ;set EEMWE (Master Write-enable) sei ;enable all interrupts ; - - - -EEPROM Data Write End - - - -
There have been many reports of EEPROM data corruption, mainly if the supply voltage is too low for the EEPROM to operate properly. According to Atmel, the solution to preventing data corruption for the on-chip EEPROM is much the same as preventing
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