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FIGURE 3.38 UART transmitter block diagram.
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UDR register to send when the stop bit is shifted out, the UDRE flag will remain set until UDR is written again. When no new data has been written, and the stop bit has been present on TXD for one bit length, the TX Complete Flag, TXC, in USR is set to 1. The TXEN bit in UCR enables the UART transmitter when set to 1. When this bit is cleared to 0, the PD1 pin can be used for general I/O. When set to 1, the UART Transmitter will be connected to PD1, which is forced to be an output pin regardless of the setting of the bit 1 in DDRD. Figure 3.39 illustrates the block diagram of the UART receiver section. The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1 to 0-transition, the receiver samples the RXD pin at samples 8, 9, and 10. If two or more of these three samples are found to be logical ones, the start bit is rejected as a noise spike and the receiver starts looking for the next 1 to 0-transition. If, however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 8,
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FIGURE 3.39 UART receiver block diagram.
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9, and 10. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the transmitter shift register as they are sampled. When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical zeros, the Framing Error (FE) flag in the UART Status Register (USR) is set to 1. Before reading the UDR register, the user should always check the FE bit to detect framing errors. Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically separate registers, one for transmitted data and one for received data. When UDR is read, the Receive Data register is accessed, and when UDR is written, the Transmit Data register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set to 1 ), the RXB8 bit in UCR is loaded with bit 9 in the Transmit shift register when data is transferred
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THE INTERRUPT STRUCTURE 53
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to UDR. If after having received a character, the UDR register has not been read since the last receive, the OverRun (OR) flag in UCR is set to 1. This means that the last data byte shifted into to shift register could not be transferred to UDR and has been lost. The OR bit is buffered and is updated when the valid data byte in UDR is read. Thus the user should always check the OR bit after reading the UDR register in order to detect any overruns if the baud rate is high or CPU load is high. When the RXEN bit in the UCR register is cleared to 0, the receiver is disabled. This means that the PD0 pin can be used as a general I/O pin. When RXEN is set to 1, the UART Receiver will be connected to PD0, which is forced to be an input pin regardless of the setting of the DDD0 bit in DDRD. When PD0 is forced to input by the UART, the PORTD0 bit can still be used to control the pull-up resistor on the pin. When the CHR9 bit in the UCR register is set, transmitted and received characters are 9 bits long, plus start and stop bits. The 9th data bit to be transmitted is the TXB8 bit in the UCR register. This bit must be set to the wanted value before a transmission is initiated by writing to the UDR register. The 9th data bit received is the RXB8 bit in the UCR register.
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