barcode reader using c#.net The Interrupt Structure in Software

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3.12 The Interrupt Structure
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An interrupt is a flow control mechanism that is implemented on most controllers. In a processor system interacting with the outside world, many things are happening asynchronously, e.g., the user may have pressed a switch for some action to be taken, while a data byte on the serial port may have arrived. It would be quite impossible for the processor to keep track of all the things just by querying these devices for data. Instead, it would be better if these devices could announce arrival of data. This is what the interrupt mechanism does. The peripheral device could interrupt the execution of the main program, and the processor takes time out of the normal program execution to examine the source of the interrupt and to take necessary action. After the required action is taken, the interrupted program execution is resumed. The interrupt program is just like a subroutine, except that the execution of this interrupt subroutine is not anticipated by the processor to occur at a particular moment of time. The AVR has a rich interrupt structure. Interrupt capability has been provided to most of the peripheral devices so that the main program need not poll these devices all the time. The sequence of events when an interrupt occurs is as follows:
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1. The peripheral device interrupts the processor. 2. Current instruction execution is completed. 3. The address of the next instruction is stored on the stack (either a hardware stack or a
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software stack).
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4. Address of the ISR (interrupt subroutine) are loaded into the program counter. 5. The processor executes the ISR. 6. The ISR execution completion is indicated by the RETI instruction (return from
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interrupt).
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7. The processor loads the program counter with the value stored on the stack and normal
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program execution resumes.
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54 THE AVR MICROCONTROLLER ARCHITECTURE
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Since the interrupt can occur at any time, the processor status (flags, etc.) must be saved so that normal program execution can resume after the ISR is completed. The processor status is contained in the SREG register. The ISR must save the SREG before executing any other instruction, and before returning control to the main program, must restore the SREG register. This can be done in two ways: either the SREG is copied into another register, say R1, which must not be used for any other purpose, and before the ISR executes the RETI instruction, R1 is copied back into SREG. Another way to save the SREG is to save it on the stack (using the PUSH SREG instruction) and then before executing the RETI instruction, the SREG value is copied back from the stack (using the POP SREG instruction). This method is only possible for those processors that have a software stack. AT90S1200, for example, cannot use this method of saving the SREG register. Figure 3.40 illustrates how the main program is interrupted. It is also possible to interrupt an ISR if another interrupt occurs and the global interrupt flag has been set to 1 within ISR for interrupt1 (using the SEI instruction). In that case, the ISR1 is interrupted and another ISR, ISR2, executes. ISR1 execution resumes after ISR2 finishes, and after ISR1 completes execution, the main program resumes execution. Normally, after an interrupt occurs and is being serviced by the corresponding ISR, the global interrupts are disabled automatically (equivalent to executing the CLI instruction); however, it is possible to enable interrupts while an ISR is executing by executing the SEI instruction in the ISR. If another interrupt occurs during the time when an ISR is already operating, then it will be serviced by interrupting the original ISR. The priority of interrupts is determined by the way the interrupt vectors are assigned. An interrupt vector at a lower address in the program memory has a higher priority. The priority of interrupt is used to decide which interrupt gets serviced first if more than one interrupt is pending at any moment of time. This situation can arise when global interrupts have been disabled in a system to allow some critical section of the program to execute. After the critical section is completed, the program enables the global interrupts. Now, during the time the critical section was being executed, two interrupts, an external Interrupt0 and UART Rx Complete interrupt occurred. Then, since the external Interrupt0 has a higher priority than the UART interrupts, the ISR corresponding to the external Interrupt0 will be executed, and after that, the ISR for the UART interrupt will execute. The lowest program memory addresses are assigned for reset and interrupt vectors. For the AT90S2313, these vectors are corresponding program memory addresses as follows:
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