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FIGURE 3.40 Nested interrupt execution.
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rjmp RESET rjmp EXT_INT0 rjmp EXT_INT1 rjmp TIM_CAPT1 rjmp TIM_COMP1 rjmp TIM_OVF1 rjmp TIM_OVF0 rjmp UART_RXC rjmp UART_DRE rjmp UART_TXC rjmp ANA_COMP
; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ; Timer1 Capture Handler ; Timer1 Compare Handler ; Timer1 Overflow Handler ; Timer0 Overflow Handler ; UART RX Complete Handler ; UDR Empty Handler ; UART TX Complete Handler ; Analog Comparator Handler
A very important consideration while using interrupts is how fast a processor can respond to an interrupt. This is largely decided by the processor architecture. For the AVR controllers, the interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. Four clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this four-clockcycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is normally a relative jump to the interrupt routine, and this jump takes two clock cycles. If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is served. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. A sample program to understand the interrupt operation using Timer1 interrupt is available in the code directory as file intr_ex.asm. The hardware for this program is the same as in Figure 6.47 in 6 (and you don t need the EEPROM). Just connect the processor to the PC serial port and you can see the bit PORTB6 toggling at the rate of the Timer1 interrupt (in multiples of 10 ms).
3.13 The Internal Watchdog Timer
A watchdog timer is a controlled timer that is used as a wakeup device in case the software is lost in some infinite loop or in case of faulty program execution. The watchdog timer has an output that has the capability to reset the controller. Figure 3.41 illustrates the watchdog timer block diagram.
56 THE AVR MICROCONTROLLER ARCHITECTURE
FIGURE 3.41 Watchdog timer block diagram.
The watchdog timer is clocked from a separate on-chip RC oscillator. By controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted as illustrated in Table 3.8. The watchdog reset intervals are also power-supply dependent. The watchdog reset instruction, WDR, resets the watchdog timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another watchdog reset, the AVR controller is reset and starts executing the program again from the reset vector. To prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is disabled, as illustrated in the description of the Watchdog Timer Control Register section.
3.14 Power-Down Modes of Operation
The AVR controller offers a variety of power-consumption-reducing schemes. To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file, SRAM, and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the reset vector. When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the idle mode, stopping the CPU but allowing timer/counters, watchdog, and the interrupt system to continue operating. This enables the MCU to wake up from externally triggered interrupts as well as internal ones like timer overflow interrupt and watchdog reset. If wakeup from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the ACD bit in the analog comparator control and status register ACSR. This will reduce power consumption in idle mode. When the MCU wakes up from idle mode, the CPU starts program execution immediately. When the SM bit is set (one), the SLEEP instruction forces the MCU into the powerdown mode. In this mode, the external oscillator is stopped, while the external interrupts
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