read barcode from image c#.net DIFFERENT TYPES OF AVR CONTROLLERS 57 in Software

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DIFFERENT TYPES OF AVR CONTROLLERS 57
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and the watchdog (if enabled) continue operating. Only an external reset, a watchdog reset (if enabled), or an external level interrupt on INT0 or INT1 can wake up the MCU. Note that when a level-triggered interrupt is used for wake up from power down, the low level must be held for a time longer than the reset delay time-out period tTOUT. Otherwise, the device will not wake up. Figure 3.42 illustrates the current consumption by a Tiny22 processor during the active and power-down modes of operation.
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3.15 Different Types of AVR Controllers
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The AVR family offers many controllers with different peripheral resources, program memory, and packaging styles. Table 3.11 illustrates the available controllers and their features.
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Active and Power Down mode current consumption in AVR Tiny22 processor (internal oscillator mode)
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Active mode (3.57 mA) Power Down mode (120 uA)
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FIGURE 3.42 Current consumption by a Tiny22 processor in internal oscillator mode during the active and power down mode.
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TABLE 3-11 PART AVR CONTROLLER SELECTION TABLE PINS SPEED FLASH EEPROM RAM UART ADC
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90S1200 90S2313 90S2323 90S2343 90S2333 90S4433
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20 20 8 8 28 28
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16 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz
1K 2K 2K 2K 2K 4K
64 128 128 128 128 256
0 128 128 128 128 128
No Yes No No Yes Yes
No No No No Yes Yes
58 THE AVR MICROCONTROLLER ARCHITECTURE
PART
PINS
SPEED
FLASH
EEPROM
UART
90S4414 90S8515 90S4434 Mega103 Mega603 Tiny10 Tiny12 Tiny13 Tiny22
40 40 40 64 64 8 8 8 8
10 MHz 8 MHz 10 MHz 6 Mhz 6 Mhz 10 MHz 10 MHz 10 MHz 10 MHz
4K 8K 4K 128 K 64 K 1K 1K 2K 2K
256 512 256 4096 2048 64 64 128 128
256 512 256 4096 4096 0 0 128 128
Yes Yes Yes Yes Yes No No No No
No No Yes Yes Yes No No No No
THE AVR INSTRUCTION SET
he Instruction set of a processor or a controller is like the vocabulary of the processor. Each instruction controls some part of the processor and allows the programmer to manipulate data in the memory as well as input and output devices. The instructions of the processor can be categorized in many different ways based on how the instructions access data and operate upon it. This is called the program and data addressing modes of the processor.
4.1 Program and Data Addressing Modes
The various AVR instructions can be categorized in about 10 different addressing modes. Each instruction has an opcode that indicates to the control logic of the processor what to do. The other part of the instruction is the operand, on which the opcode operates.
REGISTER DIRECT (SINGLE REGISTER)
The Register Direct instructions can operate on any of the 32 registers of the register file. It reads the contents of a register, operates on the contents of the register, and then stores
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60 THE AVR INSTRUCTION SET
the result of the operation back into the same register. Figure 4.1 illustrates the source and destination for these types of instructions. The format of the instruction is: Mnemonic Destination Register. Examples of these instructions are as follows. Rd is any register from the register file and is the destination (as well as the source) register for the operation. COM Rd: 1 s complement (invert all the bits) of the register Rd is stored back in register Rd. INC Rd: Increments the contents of Rd by one. DEC Rd: Decrements the contents of Rd by one. TST Rd: Test for zero or negative contents of the Rd register. CLR Rd: Loads $00 into the Rd register. SER Rd: Loads $FF into the Rd register. LSL Rd: Shifts the contents of register Rd one place to left. A 0 is shifted in bit position 0, and the contents of bit7 are copied to the Carry flag. LSR Rd: Shifts the contents of register Rd one place to Right. A 0 is shifted in bit position 7, and the contents of bit0 are copied to the Carry flag. ROL Rd: Rotate Rd register contents left through the carry. Carry flag goes to bit0, and bit7 goes into the carry. ROR Rd: Rotate Rd register contents right through the carry. Carry flag goes to bit7, and bit0 goes into the carry.
FIGURE 4-1 Direct single register access.
PROGRAM AND DATA ADDRESSING MODES 61
ASR Rd: Arithmetic Shift right the contents of the Rd, keeping the bit7 at the same place. This achieves a signed divide by two for each shift. Swap Rd: Swap nibbles of the register Rd.
REGISTER DIRECT (TWO REGISTERS)
In these types of instructions, two registers are involved. The two registers are named as the source register, Rs, and the destination register, Rd. The instruction reads the two registers and operates on their contents and stores the result back in the destination register. Figure 4.2 illustrates the source and destination for these types of instructions. Example instructions are: ADD Rd, Rs; SUB Rd, Rs; AND Rd, Rs; MOV Rd, Rs; OR Rd, Rs;
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