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These instructions are used to access the I/O space. The I/O registers can only be accessed using these instructions: In Rd, PORTADDRESS; Out PORTADDRESS, Rs. Rd, Rs can be any of the 32 registers from the register file, and the I/O registers can be any register from the entire range of $00 to $3F (a total of 64 I/O registers). Figure 4.3 illustrates how such instructions operate.
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These are two word instructions. One of the words is the address of the data memory space. So a maximum of 64 Kbyte data memory can be accessed using these types of instructions.
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FIGURE 4-2 Direct double register access.
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FIGURE 4-3 Direct I/O memory access.
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The examples of these instructions are: LDS RD, K; K is a 16-bit address. STS K, Rs; Figure 4.4 illustrates how direct data instructions operate.
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These are similar to the data direct type of instructions, except that these instructions are one word each, and a pointer register (X, Y, or Z) is used that has the base address of the data memory. To the base address in the pointer register, an offset can be added, as well as some increment/decrement operations on the pointer contents. Examples of these instructions are: LD Rd, X; X is the pointer register (register pair R26, R27); LD Rd, X ; Rd is the destination register and it is loaded with the contents of the data memory pointed to by the X register, and after the memory is accessed, the X register is incremented. ST X, Rs; ST X , Rs; ST-Y, Rs; and so on. Figure 4.5 illustrates how one variant of indirect data instructions operate.
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INDIRECT PROGRAM ADDRESSING
In these types of instructions, the Z register is used to point to the program memory. Up to 64 Kbytes of program memory can be accessed with the 16-bit Z register. Examples of these types of instructions are: IJMP and ICALL. Figure 4.6 illustrates how indirect program addressing instructions operate.
RELATIVE PROGRAM ADDRESSING
These instructions are of the type RJMP and RCALL, where an offset of / 2K to the program counter is used. Figure 4.7 illustrates how relative program addressing instructions operate.
ARITHMETIC AND LOGIC INSTRUCTIONS 63
FIGURE 4-4 Direct data memory access.
FIGURE 4-5 Indirect data memory access.
4.2 Arithmetic and Logic Instructions
1. ADD Rd, Rs; Add without Carry. Rd Rd Rs;
Flags affected: Z, C, N, V S, H. , Clocks: 1. Example: ADD R2, R3
64 THE AVR INSTRUCTION SET
FIGURE 4-6 Indirect program memory instructions.
FIGURE 4-7 Indirect program memory instructions.
2. ADC Rd, Rs; Add with Carry. Rd
Flags affected: Z, C, N, V S, H. , Clocks: 1. Example: ADC R5, R3 3. ADIW Rd, k; Add immediate constant to Rd:Rd 1. Rd 1: Rd Flags affected: Z, C, N, V S. , Clocks: 2. Example: ADIW R26, 5 4. SUB Rd, Rs; Subtract without Carry. Rd Flags affected: Z, C, N, V S, H. , Clocks: 1. Example: SUB R1, R3 Rd Rs; Rd 1:Rd k;
ARITHMETIC AND LOGIC INSTRUCTIONS 65
5. SUBI Rd, k; Subtract immediate without Carry. Rd Flags affected: Z, C, N, V S, H. , Clocks:1. Example: SUBI R5, 10 6. SBCI Rd, k; Subtract immediate with Carry. Rd Flags affected: Z, C, N, V S, H. , Clocks: 1. Example: SBCI R10, 2 7. SBC Rd, Rs; Subtract with Carry. Rd Flags affected: Z, C, N, V S, H. , Clocks: 1. Example: SBC R5, R3 Rd Rs Rd
8. SBIW Rd, k; Subtract immediate constant from Rd:Rd Rd 1:Rd k; Flags affected: Z, C, N, V S. , Clocks: 2. Example: SBIW R26, 5 9. AND Rd, Rs; Logical AND Rd and Rs. Rd Flags affected: Z, N, V S. , Clocks: 1. Example: AND R26, R2
10. ANDI Rdx, k; Logical AND Rdx and k. Rdx
1. Rd
1: Rd
Rd & Rs.
Rd & k. Rdx is between R16 and
R31l; k is an 8-bit constant. Flags affected: Z, N, V S. , Clocks: 1. Example: ANDI R26, 5
11. OR Rd, Rs; Logical OR Rd with Rs. Rd
Rd | Rs.
Flags affected: Z, N, V S. , Clocks: 1. Example: OR R1, R2
12. ORI Rdx, k; Logical OR Rdx with k. Rdx
Rd | k. Rdx is between R16 and R31; k
is an 8-bit constant. Flags affected: Z, N, V S. , Clocks: 1. Example: ORI R16, 0b11110000
13. EOR Rd, Rs; Exclusive OR Rd with Rs. Rd
Rd Exor Rs.
Flags affected: Z, N, V S. , Clocks: 1. Example: EOR R1, R2
66 THE AVR INSTRUCTION SET
14. COM Rd; One s complement Rd. Rd
Flags affected: Z, C, N, V S. , Clocks: 1. Example: COM R1
15. NEG Rd; Two s complement Rd. Rd
Flags affected: Z, C, N, V S, H. , Clocks: 1. Example: NEG R30
16. SBR Rdx, k; Set bit(s) in Rdx. Rdx
Rdx v k. Rdx is between R16 and R31.
Flags affected: Z, N, V S. , Clocks: 1. Example: SBR R30, 5
17. CBR Rdx, k; Clear bit(s) in Rdx. Rdx
Rdx & ($FF k). Rdx is between R16 and
R31. Flags affected: Z, N, V S. , Clocks: 1. Example: CBR R28, 5
18. INC Rd; Increment contents of Rd. Rd
Flags affected: Z, N, V S. , Clocks: 1. Example: INC R3
19. DEC Rd; Decrement contents of Rd. Rd
Flags affected: Z, N, V S. , Clocks: 1. Example: DEC R2
20. TST Rd; Test Rd for zero or minus. Rd
Rd & Rd.
Flags affected: Z, N, V S. , Clocks: 1. Example: TST R2
21. MUL Rd, Rs; Unsigned multiplication of Rd and Rs. The result is stored in R1:R0.
R1: R0 Rd Rs. Flags affected: Z, C. Clocks: 2. Example: MUL R3, R2
22. MULS Rd, Rs; Signed multiplication of Rd and Rs. The result is stored in R1: R0.
R1: R0 Rd Rs. Flags affected: Z, C. Clocks: 2. Example: MULS R4, R5
PROGRAM CONTROL INSTRUCTIONS 67
23. MULSU Rd, Rs; Signed multiplication of Rd (signed) and Rs (unsigned). The result
is stored in R1: R0. R1: R0 Flags affected: Z, C. Clocks: 2. Example: MULSU R4, R5
24. FMUL Rd, Rs; Unsigned fractional multiplication of Rd(1.7 format) and Rs(1.7 for-
mat). The result is stored in R1: R0(1.15 format). R1: R0 Flags affected: Z, C. Clocks: 2. Example: FMUL R30, R31 mat). The result is stored in R1:R0 (1.15 format). R1: R0 Flags affected: Z, C. Clocks: 2. Example: FMULS R4, R5
25. FMULS Rd, Rs; Signed fractional multiplication of Rd (1.7 format) and Rs (1.7 for-
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