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data memory(X). X is the pointer reg-
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data memory (Y). Y is the pointer register pair R28:
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1. Y is the pointer reg-
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Y; Load Indirect. Y ister pair R28: R29. Flags affected: None. Clocks: 2. Example: LD R15, Y
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11. LDD Rd, Y q; Load Indirect with displacement. Rd
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q). Y is the
pointer register pair R28: R29. Flags affected: None. Clocks: 2. Example: LD R15, Y 2
12. LD Rd, Z; Load Indirect. Rd
data memory(Z). Z is the pointer register pair R30:
R31. Flags affected: None. Clocks: 2. Example: LD R1, Z
13. LD Rd, Z ; Load Indirect. Rd
data memory(Z), Z
1; Z is the pointer reg-
ister pair R30: R31. Flags affected: None. Clocks: 2. Example: LD R15, Z
14. LD Rd,
Z; Load Indirect. Z ister pair R30: R31. Flags affected: None.
1, Rd
data memory(Z). Z is the pointer reg-
74 THE AVR INSTRUCTION SET
Clocks: 2. Example: LD R15,
Z data memory(Z q). Z is the
15. LDD Rd, Z q; Load Indirect with displacement. Rd
pointer register pair R30: R31. Flags affected: None. Clocks: 2. Example: LD R15, Z 5
16. STS Rs, k; Store Immediate. data memory(k)
Flags affected: None. Clocks: 2. Example: STS $5300, R1
17. ST X, Rs; Store Indirect. data memory(X)
Rs. X is the pointer register pair R26:
R27. Flags affected: None. Clocks: 2. Example: ST X, R1
18. ST X , Rs; Store Indirect. data memory(X)
Rs, X
1. X is the pointer reg-
ister pair R26: R27. Flags affected: None. Clocks: 2. Example: ST X , R15
19. ST
X, Rs; Store Indirect. X ister pair R26: R27. Flags affected: None. Clocks: 2. Example: ST X, R11
1, data memory(X)
Rs. X is the pointer reg-
20. ST Y, RD; Store Indirect. data memory(Y)
Rs. Y is the pointer register pair R28:
R29. Flags affected: None. Clocks: 2. Example: ST Y, R1
21. ST Y , Rs; Store Indirect. data memory(Y)
Rs, Y
1; Y is the pointer regis-
ter pair R28: R29. Flags affected: None. Clocks: 2. Example: ST Y , R5
22. ST
Y, Rs; Store Indirect. Y ister pair R28: R29. Flags affected: None.
1, data memory(Y)
Rs. Y is the pointer reg-
DATA TRANSFER INSTRUCTIONS 75
Clocks: 2. Example: ST
23. STD Y
Y, R5 q) Rs. Y is
q, Rs; Store Indirect with displacement. data memory(Y the pointer register pair R28: R29. Flags affected: None. Clocks: 2. Example: STD Y 2, R8
24. ST Z, RD; Store Indirect. data memory(Z)
Rs. Z is the pointer register pair R30:
R31. Flags affected: None. Clocks: 2. Example: ST Z, R1
25. ST Z , Rs; Store Indirect. data memory(Z)
Rs, Z
1; Z is the pointer regis-
ter pair R30: R31. Flags affected: None. Clocks: 2. Example: ST Z , R5
26. ST
Z, Rs; Store Indirect. Z ter pair R30: R31. Flags affected: None. Clocks: 2. Example: ST Z, R5
1, data memory(Z)
Rs. Z is the pointer regis-
27. STD Z q, Rs; Store Indirect with displacement. data memory(Z q)
Rs. Z is the
pointer register pair R30: R31. Flags affected: None. Clocks: 2. Example: STD Z 2, R8
28. LPM; Load Program Memory. R0
Program Memory(Z). Z is the pointer register
pair R30: R31. Flags affected: None. Clocks: 3.
29. LPM Rd, Z; Load Program Memory. Rd 5 Program Memory(Z). Z is the pointer reg-
ister pair R30: R31. Flags affected: None. Clocks: 3. Example: LPM R2, Z
30. LPM Rd, Z ; Load Program Memory. Rd
Program Memory(Z), Z
1. Z is
the pointer register pair R30: R31. Flags affected: None.
76 THE AVR INSTRUCTION SET
Clocks: 3. Example: LPM R20, Z
31. IN Rd, A; Input from Input Port. Rd
I/OPort(A),
Flags affected: None. Clocks: 1. Example: IN r1, PINB
32. OUT A, Rs; Output to output Port. I/OPort(A)
Flags affected: None. Clocks: 1. Example: OUT PORTB, R16
33. PUSH Rs; Push register on STACK. STACK
Flags affected: None. Clocks: 2. Example: PUSH r1
34. POP Rd; Pop into register from STACK. Rd
STACK,
Flags affected: None. Clocks: 2. Example: POP r1
4.5 Bit and Bit-test Instructions
1. LSL Rd; Logical Shift Left. Rd(n 1) Flags affected: Z, C, N, V H. , Clocks: 1. Example: LSL r1 2. LSR Rd; Logical Shift Right. Rd(n) Flags affected: Z, C, N, V . Clocks: 1. Example: LSR r10 Rd(n); Rd(0) 0; C Rd(7).
Rd(n 1); Rd(7)
0; C
Rd(0).
3. ROL Rd; Rotate Left though Carry. Rd(0) Flags affected: Z, C, N, V H. , Clocks: 1. Example: ROL r13 4. ROR Rd; Rotate Right through Carry. Rd(7) Flags affected: Z, C, N, V . Clocks: 1. Example: ROR r10
C; Rd(n 1)
Rd(n); C
Rd(7).
C; Rd(n)
Rd(n 1); C
Rd(0).
BIT AND BIT-TEST INSTRUCTIONS 77
5. ASR Rd; Arithmetic Shift Right. Rd(n) Flags affected: Z, C, N, V . Clocks: 1. Example: ASR r10
Rd(n 1), for n
0 to 6;
6. SWAP Rd; Swap Nibbles. exchange Rd(3,2,1,0) with Rd(7,6,5,4) Flags affected: None. Clocks: 1. Example: SWAP r10 7. BSET s; Flag Set. SREG(s) Flags affected: SREG(s). Clocks: 1. Example: BSET 7 8. BCLR s; Flag Reset. SREG(s) Flags affected: SREG(s). Clocks: 1. Example: BCLR 7 1;
9. SBI A, s; Set bit s in I/O register A. I/O(A,s) Flags affected: none. Clocks: 1. Example: SBI PORTD, 7
10. CBI A, s; Clear bit s in I/O register A. I/O(A,s)
Flags affected: none. Clocks: 1. Example: CBI PORTD, 7
11. BST Rs, s; Bit Store from Rs to T flag. T
Rs(s);
Flags affected: T. Clocks: 1. Example: BST R1, 2
12. BLD Rd, s; Bit Store from T flag to Rd. Rd(s)
Flags affected: none. Clocks: 1. Example: BLD R4, 2
13. SEC; Set Carry flag. C
Flags affected: C. Clocks: 1. Example: SEC
14. CLC; Clear Carry flag. C
Flags affected: C.
78 THE AVR INSTRUCTION SET
Clocks: 1. Example: CLC
15. SEN; Set Negative flag. N
Flags affected: N. Clocks: 1. Example: SEN
16. CLN; Clear Negative flag. N
Flags affected: N. Clocks: 1. Example: CLN
17. SEZ; Set Zero flag. Z
Flags affected: Z. Clocks: 1. Example: SEZ
18. CLZ; Clear Zero flag. Z
Flags affected: Z. Clocks: 1. Example: CLZ
19. SEI; Set Interrupt flag. I
Flags affected: I. Clocks: 1. Example: SEI
20. CLI; Clear Interrupt flag. I
Flags affected: I. Clocks: 1. Example: CLI
21. SES; Set Signed Test flag. S
Flags affected: S. Clocks: 1. Example: SES
22. CLS; Clear Signed Test flag. S
Flags affected: S. Clocks: 1. Example: CLS
23. SEV; Set Two s Complement flag. V
Flags affected: V . Clocks: 1. Example: SEV
BIT AND BIT-TEST INSTRUCTIONS 79
24. CLV; Clear Two s Complement flag. V
Flags affected: V . Clocks: 1. Example: CLV
25. SET; Set T flag. T
Flags affected: T. Clocks: 1. Example: SET
26. CLT; Clear T flag. T
Flags affected: T. Clocks: 1. Example: CLT
27. SEH; Set Half Carry flag. H
Flags affected: H. Clocks: 1. Example: SEH
28. CLH; Clear Half Carry flag. H
Flags affected: H. Clocks: 1. Example: CLH
29. NOP; No Operation;
Flags affected: none. Clocks: 1. Example: NOP
30. SLEEP; Sleep;
Flags affected: none. Clocks: 1. Example: SLEEP
31. WDR; Watchdog Reset;
Flags affected: none. Clocks: 1. Example: WDR
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AVR HARDWARE DESIGN ISSUES
What does it take to get a simple AVR-based circuit up and running Well, it would take
a processor, voltage source, clock generation circuit, and a suitable reset circuit for reliable operation. Figure 5.1 illustrates this simple configuration. The external clock generation circuit is optional, as many of the AVR processors have an internal RC oscillator that is used when feasible. Let us look at these issues in some detail.
5.1 Power Source
The power source for running a processor system is a critical component. No system would run without a power supply. There are various options that the designer may consider, depending upon the application. Broadly, the choice would be dictated by whether the system is portable and hence must use a battery source or whether it is for a desktop application, where an AC power line could be used. Sometimes you may have access to an AC power line, but the battery operation may seem more convenient simply because it offers added portability and does not require a bulky transformer and associated rectifier, filter, and regulator components.
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