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I/O EXPANSION USING SHIFT REGISTER
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Figure 6.6 illustrates the scheme for a an 8-bit digital input port using an 8-bit parallel-in, serial-out shift register. This expansion scheme requires 3 I/O pins, and for the cost of 3 I/O pins, you get 8 input-only pins. The 74165 has 5 control lines: serial-in to cascade multiple shift registers, Qout, which is the shift register output, Clock Inhibit to disable clocking of the shift register, Shift/Load*, that is used to capture the input data and shift it out through the Qout pin, and the Clock input pin.
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Figure 6.6 Eight-bit digital input port using a parallel-in serial-out shift register.
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EXPANDING I/O 111
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For an 8-bit input port, we need just one 74165, and so the serial-in pin is connected to ground. The clock inhibit pin is also grounded so the clock input is always enabled. The Qout pin is connected to the PORTB7 pin for reading in the shift register data, the Clock signal pin is connected to the PORTB6 pin, and the Shift/Load* pin is connected to the PORTB5 pin. To read a byte of input data from this expansion port, the Shift/Load* pin is reset to 0 momentarily and then set to 1 . This captures the input data in an internal register in the shift register. After this, the Clock signal is pulsed and for each pulse, the PORTB7 pin is read and a bit is shifted out in an internal register. After eight such clock pulses and shifts, the entire byte from the 74165 shift register is read into the AVR processor. Similarly, Figure 6.7 illustrates an 8-bit output only port. The circuit operates similar to the input port expansion scheme, except that the PORTB7 pin is used to output data to the output shift register CD4094. Eight bits of data are shifted into CD4094, and after eight shifts, the strobe signal for the output stage latch of the CD4094 is set to 1 to transfer the shift register data to the output pins. When the data is being shifted into the shift register, the strobe signal is held at logic 0 .
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IIC EXPANDERS
In addition to the shift register method of expanding the I/O capacity of an AVR processor, there exists another method to expand I/O capacity. The idea is to use IIC bus-based I/O expander ICs. Manufacturers have perceived the need for increasing the I/O and have designed chips for the purpose. Philips, who is the developer of the IIC bus has designed
Digital Output
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 DATA OE CD4094 CLK Strobe
AVR Processor
Figure 6.7 Eight-bit digital output port using a serial-in parallel-out shift register.
112 HARDWARE AND SOFTWARE INTERFACING WITH THE AVR
many IIC I/O expanders. Figure 6.8 illustrates the block diagram of just such an I/O expander. It offers one 8-bit bidirectional port. Up to eight such ICs can be hooked on the same IIC bus to achieve more I/O capability. Figure 6.9 illustrates how the PCF8574 I/O expander IC can be connected to the AVR processor. The INT* output is connected to the INT0 input of the AVR so that by sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. This means that the PCF8574 can remain a simple slave device.
6.7 Interfacing Analog-to-Digital Converters
An analog-to-digital converter (ADC) is a device that converts analog voltage to a digital number. An ADC is used to digitize analog signals. A signal varying with time is sampled at discrete time intervals, and a number representing the amplitude of the signal at the instant is recorded. This is illustrated in Figure 6.10. The code output is on the Y axis and the time is on the X axis. The code output has eight levels, and these can be encoded with three bits. So the encoded binary number ranges from 000 to 111. There are many types of ADC techniques, and we will not go into those details. I will mention the type of ADC when we consider a particular chip. For now, let s see how the AVR processor can be used to encode an external analog signal.
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