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MAX111/MAX110 is a serial 14-bit, dual-channel ADC from Maxim. MAX111/MAX110 ADC uses an internal autocalibration technique to achieve 14-bit resolution without any external component. The ADC offers two channels of ADC conversion and operates with 650 A current, thus making it ideal for portable, battery-operated data acquisition operations. MAX111 operates from a single 5-V power supply and converts differential signals in the range of 1.5 V or differential signals in the range of 0 to 1.5 V . MAX111 can operate from an external as well as internal oversampling clock that is used for the ADC conversion. To start a conversion, digital data is shifted into the MAX111 serial register after pulling the CS low. CS can only be pulled low when BUSY is inactive. MAX111 has a fully static serial I/O shift register which can be read at any serial clock (SCLK) rates from DC to 2 MHz. Input data to the ADC is clocked in at the rising edge of the SCLK and the output data from the ADC (conversion result) is clocked out at SCLK falling edge and should be read on SCLK rising edge. The data clocked into the ADC determines the ADC operation, which could be to initiate a new conversion, calibrate the ADC, perform offset null, change ADC channel, change oversampling clock divider ratio, etc. The format of this control word is as follows:
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bit # 15 No-op bit # 7 DV2 14 NU 6 NU 5 NU 13 NU 12 11 10 9 8 CONV4 CONV3 CONV2 CONV1 DV4 4 3 2 1 0 CHS CAL NUL PDX PD
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Figure 6.19 Circuit schematic for an AT90S2313 processor interface to the MAX186 ADC.
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No-OP NU CONV1-4 DV4-2 CHS CAL NUL PDX PD
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If this bit is 1, the remaining 15 bits are transferred to the control register and a new conversion begins when CS* returns high. Not Used, should be set low. Conversion time control bits. Oversampling clock ration control bits. Input channel select, logic 1 selects channel 2, low selects channel 1. Gain Calibration bit. A high bit selects gain calibration mode. Internal Offset Null bit. Logic high selects this mode. Oscillator power down bit, selected with logic high. Analog power down bit selected with logic high.
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Figure 6.20 illustrates an AVR processor interfaced to the MAX111 ADC. The AVR controller monitors the status of BUSY* signal, which indicates if the ADC is busy with a conversion. A 0 on this pin indicates that the ADC is still converting. The program reads the status of BUSY* on the PORTD2 pin. When the program finds BUSY* at logic 1 , it pulls the CS* signal of the ADC low to start a new conversion process. It then generates 16 clock pulses on the PORTD5 pin connected to the SCLK signal pin of the ADC. Synchronized to these pulses, the program generates a serial bit stream on pin PORTD4 connected to the Din pin of the ADC. This bit stream contains the control
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+5V .1 uF Vcc(20) PD2(6) PD3(7) RESET(1) .1 uF PD5(9) PD6(11) SCLK CS* Vref Vcc Gnd 4 MHz 22 pF X2(4) Vin2PD4(8) BUSY Dout Din Vin2+ AT90S2313 Vin1+ Vin1-
X1(5) Gnd(10) 22 pF
Figure 6.20 MAX111 interface to the AVR processor.
124 HARDWARE AND SOFTWARE INTERFACING WITH THE AVR
word with the format described previously. Output data from the ADC is clocked out on Dout pin on the falling edges of the SCLK pulses. The program reads this data on the PORTD3 pin. The CS* signal connected to the PORTD6 pin is pulled up after the 16 clock pulses are generated. The ADC pulls its BUSY* signal low while the conversion is in progress. The conversion time depends upon the XCLK frequency and the format of the control word. In this circuit, the internal RC oscillator is used for the conversion clock. The converted data is clocked out in the next round of the clocking sequence by the ADC. Figure 6.21 illustrates the timing diagram of a typical conversion and readout sequence recorded on a logic analyzer. A suitable data conversion and readout driver code is included in a later project chapter. The driver program is in C .
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