read barcode from image c#.net Interfacing Digital-to-Analog Converters in Software

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6.8 Interfacing Digital-to-Analog Converters
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Digital-to-Analog Converters (DACs) are devices that function exactly opposite to the ADCs. DACs convert digital data to analog voltage (or current). Functionally, the DAC has n digital input lines and 1 output line that provides analog voltage or current. The analog output is proportional to the weighted sum of the digital inputs.
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USING PWM FOR A DAC
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Pulse Width Modulation (PWM) technique can be used easily to create a DAC, especially since many of the members of the AVR processor family are equipped with on-chip PWM. In PWM, a digital signal of fixed frequency is generated. The pulse width of the signal is changed according to the requirement. Ideally, it should be possible to vary the width to any arbitrary value. However, with a counter-based PWM, the change can be only as much as the resolution of the counter. A PWM implemented using an 8-bit counter can only change the pulse width by 0.4% approximately (1 bit in 255). By employing a low-pass filter at the output of a PWM wave, the average value of the signal is extracted. The average value of a digital signal is equal to the duty cycle of the waveform. Figure 6.22 illustrates a 2-bit PWM signal. Figure 6.23 illustrates a DAC using the built-in PWM generator on output PORTB3 pin and an external RC filter. The RC filter has a bandwidth of about 16 Hz for the values illustrated. The Timer1 can be clocked at the system clock frequency of 4 MHz as illustrated, and for an 8-bit PWM, the PWM frequency will be about 7800 Hz. The RC filter will cleanly filter out the high-frequency components, and a clean DC value will be produced.
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R-2R LADDER DAC
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Using only two different values of resistors, it is possible to build a simple R-2R ladder DAC of reasonable linearity. Figure 6.24 illustrates a R-2R ladder DAC connected to the PORTB of the AT90S1200. To use the DAC, the following code can be used.
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ADC reads data at the rising edge
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SCLK AVR sets up data before SCLK rising edge
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ADC outputs converted data at the falling edge
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Program prepares for readout and next conversion CS* ADC conversion begins
ADC conversion over BUSY*
Figure 6.21 Timing diagram of the conversion and readout process of the MAX111.
126 HARDWARE AND SOFTWARE INTERFACING WITH THE AVR
Figure 6.22 A continuously varying PWM signal. The average value of the signal changes by 25% in each period.
+5V AT90S2313 .1 uF Vcc(20) PB3(15) RESET(1) .1 uF X2(4) X1(5) 4 MHz 22 pF 22 pF Gnd(10) 1 uF 10 KOhm DAC Output
Figure 6.23 PWM DAC using an AT90S2313 and an output RC filter.
.include 1200def.inc .def DACVALUE=r17 .def temp =r18 init_portb: ldi temp, $FF out DDRB, temp load_dac: out PORTB, DACVALUE ;Register with the DAC value ;Initialize PORTB as output ;output value to the DAC
6.8.3 MAX521 DAC
MAX521 is a voltage output DAC and has a simple 2-wire digital interface. These 2 wires can be connected to more MAX521s (total up to 4). The IC operates from a single 5-V supply. Even with a 5-V supply, the outputs of the DACs can swing from 0 to 5 V The IC has 5 . reference voltage inputs that have a range that can be set to anywhere between 0 to 5 V . Figure 6.25 illustrates the block diagram of the IC. Table 6.2 lists the signals of the MAX521 DAC IC. The MAX521 has five reference inputs. The first four DACs each have independent reference inputs, and the last four share a common reference voltage input. The digital interface allows the IC to communicate to the host at a maximum of 400 Kbps. The input of the DACs have a dual data buffer. One of the buffer outputs drives the DACs while the other can be loaded with a new input. All the DACs can be set to a new value independently or simultaneously. The IC can also be programmed to a low-power mode, during which time the supply current is reduced to 4 A only. The power-on reset circuit inside the IC sets all of the DAC outputs to 0 V when power is initially applied.
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