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Figure 6.24 R-2R ladder DAC implementation with an AVR controller.
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The output of an 8-bit DAC is Vout = Vref (input/256) where input is an 8-bit number and Vref is the reference voltage for the channel.
DATA TRANSFER TO A MAX521
The MAX521 uses a simple two-wire interface. Up to four MAX521s can be connected to one set of these two-wire interfaces. This means that a host system with two output lines can be used to program up to 32 DACs! To send commands and data to MAX521, the host sends logic sequences on the SDA and SCL lines. Otherwise, these lines are held to 1 . The two-wire interface of MAX521 is compatible with the I2C interface. To maintain compatibility with I2C, external pull-up resistors on the SDA and SCL lines would be required. Otherwise, these resistors are not required. MAX521 is a receive-only device, so it cannot transmit any data. The host only needs two output signal lines for SDA and SCL signals. The SCL clock frequency is limited to 400 kHz. The host starts communication by first sending the address of the device followed by the rest of the information, which could be a command byte or a command byte
128 HARDWARE AND SOFTWARE INTERFACING WITH THE AVR
MAX521
SDA SCL AD1 AD0
dac_out_0 dac_out_1 dac_out_2 dac_out_3 dac_out_4
REF0 REF1 REF2 REF3 REF4
dac_out_5 dac_out_6 dac_out_7 DGND AGND
Figure 6.25 Block diagram of MAX521 DAC.
and data byte pair. Each such transmission begins with a START condition as illustrated in the timing diagram in Figure 6.26, followed by the device address (called the slave address) and command-byte, data-byte pairs or command byte alone. The end of transmission is signaled by the STOP condition on the SDA and SCL lines. The SDA signal is allowed to change only when the SCL signal is low, except during the START and STOP conditions. For the START condition, the SDA signal makes a high to low transition while the SCL signal is high. Data to the MAX521 is transmitted in 8-bit packets (which could be the address byte, the command byte, or the data byte) and it needs nine clock pulses on the SCL signal line. During the ninth SCL pulse, the SDA line is held low, as illustrated in the timing diagram. The STOP condition is signaled by a low to high transition on the SDA signal line when the SCL signal is held high. The address and command bytes transfer important information to MAX521. The address byte is needed to select one out of a maximum of four devices that could be connected to the SDA-SCL signal lines. After the host starts the communication with the START condition, all the slave devices on the bus (here the bus is referred to the SDA and SCL signal lines) start listening. The first information byte is the address byte. The slave devices compare the address bits AD0 and AD1 with the AD0 and AD1 pins condition on the IC. In case a match occurs, the subsequent transmission is for that slave device. The next transmission is either a command byte or a command-byte, data-byte pair. In either case, the data byte, if at all, follows the command byte, as illustrated in Figure 6.27. Table 6.3 lists the bit sequence of the command byte and the function of each bit. All the possible combinations of address byte, command byte, and data byte to a MAX521 are:
INTERFACING DIGITAL-TO-ANALOG CONVERTERS 129
TABLE 6-2 SIGNAL NAME
SIGNAL DESCRIPTION OF THE MAX521 DAC FUNCTION
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 REF0 REF1 REF2 REF3 REF4 SCL SDA AD0 AD1 Vdd DGNC AGND
DAC0 voltage output DAC1 voltage output DAC2 voltage output DAC3 voltage output DAC4 voltage output DAV5 voltage output DAC6 voltage output DAC7 voltage output Reference voltage input for DAC0 Reference voltage input for DAC1 Reference voltage input for DAC2 Reference voltage input for DAC3 Reference voltage input for DACs 4, 5, 6, and 7 Serial Clock input Serial Data input Address input 0. Sets IC s slave address Address input 1. Sets IC s slave address Power supply, Digital ground Analog ground 5 volts
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