read barcode from image c#.net Implementing a Finite State Machine in Software

Generator Code128 in Software Implementing a Finite State Machine

6.18 Implementing a Finite State Machine
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A finite state machine (FSM) is a formal concept with many applications. In general, a finite state machine is a device which has some inputs and some outputs. It stores the state of the machine, and depending upon the inputs, changes the state value. The outputs depend upon the state value. FSM has:
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1. 2. 3. 4.
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A set of finite states. Inputs. A transition function for each state. Outputs.
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IMPLEMENTING A FINITE STATE MACHINE 153
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FSM has great applications in pattern recognition, vending machine applications, etc. You can create a traffic light controller modeled on the FSM concept. The first step in modeling the requirement as an FSM is to create a state transition table and an output table as illustrated in Tables 6.4 and 6.5. Another way is to create a bubble diagram description as illustrated in Figure 6.52. Some of the transitions from one state are conditional, while many others are unconditional. It is valid to have an FSM with all unconditional transitions. An ordinary binary counter is an example of an FSM with unconditional state transitions. The counter just hops from one state to the next and then resets to the starting state. The minimum time for which the FSM remans in a state is determined by the clock period of the system. In a microcontroller-based system, you could put appropriate delay routines between each transition. The state of the FSM is maintained with the help of a variable (in a digital circuit, with the help of a register). It is important that all the possible states of the register are accounted for and, importantly, after power on, the register (or the variable) must be initialized with a default state, otherwise the FSM will not work at all. A test code for implementing a finite state machine is available in the code directory in the file fsm.asm.
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TABLE 6-4
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STATE TRANSITION NEXT STATE (NS)
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CURRENT STATE
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S0 X SO X S1 X
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0 and Y 1, NS
0, S0 0, 1,
1 and Y
NS NS NS NS X X
S2 S3 S3 S4 1, NS 0, NS S4 S0
S1 X 1 and Y S2 S3 S4 S4
TABLE 6-5
STATE OUTPUT
STATE OUTPUTS
SO A S1 A S2 A S3 A S4 A
0, B 1, B 1, B 0, B 1, B
23 23 32 22 44
154 HARDWARE AND SOFTWARE INTERFACING WITH THE AVR
X=1 Reset S0 A=0 B=23 X=0 S1 A=1 B=23 X=1, Y=0 X=1, Y=1 S2 A=1 S3 A=0 B=22 B=32
X=0, Y=0
S4 A=1 B=44 X=1
Figure 6.52 A bubble diagram description of a state machine.
6.19 Generating Random Numbers
Many applications such as toys and test pattern generators require random numbers. While it is almost impossible to generate a truly random number, one can approximate with a pseudorandom number. One popular way to generate a pseudorandom number is to read the contents of a freerunning counter. This is a simple scheme and can be easily implemented on the AVR controller with no extra hardware. Timer0 (or Timer1) is clocked at a certain clock frequency derived out of the system clock. Then, to get a random number, the Timer0 (or Timer1) register (TCNT0 or TCNT1) is read and what you get is a pseudorandom number. This scheme is used in the Dice project chapter. Another way to generate a pseudorandom number is to use the concept of Linear Feedback Shift Register (LFSR). LFSRs are ordinary shift registers with some outputs (called taps) feeding the input (see Figure 16-3 in 16). LFSRs have an interesting property that if the feedback taps are chosen carefully, then outputs cycle through 2n 1 sequences, for an n-bit LFSR. The sequence then repeats after 2n 1 instances. If the output sequences are observed, they appear to be random. An 8-bit LFSR is illustrated in Figure 16.3. An 8-bit LFSR will have a sequence length of 255. Similarly, a 16-bit LFSR would have a length of 65535 and so on.
GENERATING RANDOM NUMBERS 155
The LFSR can be easily implemented on the AVR controller. The LFSR must be initialized with a nonzero seed value. After the LFSR is initialized, it is clocked by shifting the values to the left and loading a new bit into the bit0 of the shift register. The new bit that is loaded into the bit0 of the shift register is calculated by XORing the bits at the selected taps of the LFSR. All of these operations can be implemented using the AVR instructions. A working example of an 8-bit LFSR implemented on the AVR controller is presented in the electronic lock project chapter.
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