IIC Bus in Software

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7.6 IIC Bus
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The IIC or I2C (Inter IC) bus is a popular bus for peripheral expansion and inter IC control. It was designed and propagated by Philips for use in their consumer products.
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FIGURE 7.8 Data write and read on an SPI bus.
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IIC BUS 165
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I2C is a two-wire bus interface with communication lines called a Serial Data Line (SDA) and a Serial Clock Line (SCL). Each device connected on the bus is software addressable by a unique address. On the bus there exists a master-slave relationship between the devices. The data transferred between the devices is in multiples of 8 bits. The data transfer rate is 100 Kbit/s in standard modes, 400 Kbit/s in fast mode, and 3.4 Mbit/s in high-speed mode. Figure 7.9 shows how various components connect to each other on a I2C bus. Of course, these components need to have the IIC bus interface. A complete system usually consists of a microcontroller and other peripheral devices. The communication on a IIC bus is initiated by the bus master (Figure 7.10). The master generates clock signals (SCL) to permit data transfer. At this time, the device that is addressed is a slave. All communication starts with a START condition and ends with a STOP condition, as illustrated in Figure 7.11. Thus these lines cannot be shared with any other non-IIC capable device except in a very simple case of a fixed master and slave, which is discussed in a later project chapter.
SDA SCL
Controller
EEPROM
DISPLAY
FIGURE 7.9 IIC bus application.
Data line stable
SDA Valid Data
change of data allowed
FIGURE 7.10 Bit transfer on an IIC bus.
166 COMMUNICATION LINKS FOR THE AVR PROCESSOR
START condition
STOP Condition
FIGURE 7.11 START and STOP conditions on an IIC bus.
Any number of bytes can be transferred between the master and the slave, depending upon the requirement, and it varies from device to device. But each byte has an acknowledge bit, thus each byte transfer requires nine clock cycles. The receiver must pull the SDA bit down to logic 0 during the acknowledge clock pulse (i.e., SDA is low when the acknowledge clock pulse is high). The AVR processor is not equipped with an integrated IIC port but can communicate with any IIC interface using ordinary port lines and suitable driver software. Besides, interfacing to many peripherals, the AVR can use IIC expanders to increase I/O capability with a minimum of port lines. Philips offers many such port expanders.
7.7 PC Parallel Port
The Parallel Port is one of the ubiquitous ports on the PC. Originally meant to be used for connecting printers to the PC, its use has proliferated extensively. It is often used to connect external disk drives (the ZIP drive is a common example), network controllers, scanners, data acquisition systems, electronic locks (more on that in a later chapter), etc. The AVR can be used to control applications that need PC connectivity. We have a complete chapter that shows how the AVR can be connected to the PC parallel port, but in this section, we just look at the features of the parallel port and understand what can be done with this interface. Figure 7.12 illustrates the inner detail of the parallel port. In reality, the parallel port is not just a single port but a composite of three ports. These ports are:
1. The 8-bit DATA port as an output port. 2. The 4-bit CONTROL port as an output port. 3. The 5-bit STATUS port as an input port.
The port signals are available on a 25-pin D type female connector on the PC, as illustrated in Figure 7.12. Further, the DATA port has two ports, one output port and another input port at the same address. This input port at the DATA port address is really used to read the state of the DATA port pins and is often called the read-back port. Similarly, the output CONTROL
PC PARALLEL PORT 167
25 Pin D type output Connector Data Bus (D7:D0) Data Bits Command Decoder Control Bits IOR*, IOW* Data Write Data Read Control Write A9 to A0 Address Bits Control Read Status Read IRQ5 / IRQ7 Status Port (5 bits) PC System Bus Tri-state buffer #4 Buffer #3 OE* Buffer #2 OE* Latch #2 IRQ Enable Buffer #1 OE* Latch #1 Data Port (8 bits) Control Port (4 bits) OC Drivers
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