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;now check if the number is less than $06 compa: cpi r18, $06 brlo enough ;yes, then nothing more ;prepare to output it ;else clc ;clear carry for sub sbci r18, $06 ;and subtract $06 rjmp compa ;do it till the remainder is ;less than $06 enough: cpi r18, $00 ; OK, now the number in r18 is ; between 0 and 5 ;The following piece of code makes this program ugly ;The identification of the number and display can be handled ;more cleverly as in bad_dice.asm brne not_0 ;number is not zero ldi r18, 0b11111110 ;number is 0, so display 1 on the out PORTB, r18 ;LEDs, i.e. light up LED B2 rjmp get_t not_0: cpi r18, $01 ;check if the number in r18 is 1 brne not_1 ldi r18, 0b11111101 ;yes, so light up B1 and B3 out PORTB, r18 rjmp get_t not_1: cpi r18, $02 ;check if it is 2 brne not_2 ;no it is not ldi r18, 0b11111100 ;yes, it is. so light up B1 and B3 out PORTB, r18 rjmp get_t not_2: cpi r18, $03 brne not_3 ldi r18, 0b11111011 out PORTB, r18 rjmp get_t not_3: cpi r18, $04 brne not_4 ldi r18, 0b11111010 out PORTB, r18 rjmp get_t not_4: ldi r18, 0b11111001 out PORTB, r18 rjmp get_t ;Delay subroutine ;uses registers r16 and r18 ;values are set arbitrarily delay: ldi r16, 0b11111100 loophere: ldi r18, 0b10001110 decrement: dec r18 brne decrement dec r16 brne loophere ret ;returns when a key on PD0 is pressed and released ;till then it loops waiting for the key press sw_input: in r16, PIND ;input PORTD pin value andi r16, 0b00000001 ;isolate PD0 state brne sw_input ;if switch is not pressed, loop back rcall delay ;if pressed, then wait some time to ;ward off the switch bounces pin_0: in r16, PIND ;now check if the switch is released andi r16, 0b00000001 breq pin_0
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;switch is now released..go back
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The code in bad_dice.asm is the same as in ugly_dice.asm, except for the part that displays the resulting number (between 0 and 5). This code is as follows:
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;code segment from bad_dice.asm enough: ldi r16, $01 ;since the number is between 0 and 5 ;add 1 to make it between 1 and 6 add r18, r16 com r18 ;the output display LEDs are arranged ;as active low, so complement the resulting ;number ori r18, 0b11111000 ;set the other unused port pins ;to an inactive state out PORTB, r18 ;display it! rjmp get_t ;that it! go get more
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The program uses free-running Timer0 to get the randomness. However, it is possible to use other methods of random number generation; a prominent one is to use Linear Feedback Shift Register (LFSR) as outlined in a previous chapter. The advantage of the LFSR method is that it only requires a seed to arm the LFSR, and then it will churn out random numbers. For this simple case, where the Timer0 is not going to be used for any other task and is always available, we could use it full time. The Timer0 is clocked at 1/1024 the clock frequency, and since the state of the timer is not known to the user, reading it gives a certain randomness suitable for our purpose. The program in good_dice.asm builds upon the code in bad_dice.asm by adding an interrupt subroutine that occurs every time TCNT0 overflows. With a clock input to the counter of clk/1024, this occurs every 128 ms for a 2.000-MHz clock. The initialization code in good_dice.asm initializes three registers as low_timer, med_timer, and high_timer to zero. The interrupt subroutine increments these registers each time the timer overflow occurs. By looking at the values in med_timer (you can modify the Timer0 ISR so that it powers down after a longer time), the Timer0 ISR determines whether to blank off the display with power-down sleep or not. The Timer0 interrupt subroutine from good_dice.asm is illustrated below.
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;Timer0 ISR from good_dice.asm ;low_timer, med_timer and high_timer are three registers ;that hold elapsed time. These registers are cleared to zero ;by main program every time a key is pressed, else their value ;builds up and when it exceeds certain value, this ISR powers ;down and puts the processor to sleep Timer_int: in save_status, SREG ;save status in reg save_status cpi med_timer, $01 ;compare med_timer to 01 brne skip_it ;is equal then prepare to power ;down ldi temp, 255 ;tri-state all outputs out PORTB, temp ;configure all ports as O/P out PORTD, temp ;and set all values to 1 out DDRD, temp
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