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Creating Code 128A in Software FIGURE 13.3 Photograph of the kitchen timer.

FIGURE 13.3 Photograph of the kitchen timer.
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TESTING 243
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FIGURE 13.4 Photograph of a pair of thumb-wheel switches
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AVR PROJECT 5: RADIO BEACON CONTROLLER
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14.1 At a Glance
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In this chapter we consider the following issues:
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1. 2. 3. 4. 5.
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What is a radio beacon What is a radio beacon used for How to build a radio beacon controller. Details of an efficient and compact single-chip radio beacon controller. How to adapt the controller for your application.
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14.2 Introduction
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Merriam Webster s Collegiate Dictionary defines a beacon as a signal fire or other signal commonly on a hill, tower, or pole for guidance. A radio beacon is a radio transmitter emitting signals for guidance of an aircraft. However, a radio beacon is used for more than aircraft guidance. A radio beacon is usually put on scientific balloons, rockets, etc., for identification as well as help in locating the object (i.e., the balloon or the rocket). Usually the beacon
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246 AVR PROJECT 5: RADIO BEACON CONTROLLER
outputs a short message over and over again, which drives an appropriate radio transmitter. In amateur radio, radio beacons have been used for quite some time. These beacons usually transmit Morse code at 22 words per minute, transmitting their call sign in 10-dB power, which is very useful for the purpose of S meter calibration and for judging the band conditions. These beacons usually transmit every three minutes. A radio beacon consists of a radio transmitter capable of transmitting at the required radio frequency and required output power. The transmitter is driven by a suitable controller that stores the guidance message. Since the radio beacon is located on unattended sites, an important consideration is to optimize available power in transmitting the guidance signal. A low-power controller that consumes as little power as possible is desirable. Figure 14.1 illustrates the block diagram of a radio beacon. The controller for a beacon can be built using a microcontroller for programmability and low-power operation.
14.3 Design Specifications
We are looking for the design of a low-power programmable controller for a radio beacon. The controller will be able to output a stored message in the form of Morse code, which will be repeated every three minutes. The repetition rate should be programmable, and it should be able to easily change the stored message. The controller should be as small as possible and should implement power-down modes of operation to minimize power consumption. The controller should work off a wide range of supply voltage. Let us see how our AVR-processor-based design meets these specifications.
14.4 Design Description
The primary requirement for a radio beacon controller is to be able to operate on as little power as possible. The controller is active for a very short time in a whole period. If we decide to operate the beacon every three minutes, then the beacon will transmit the signal for a few seconds, and after that it will be passive. Therefore, to have a controller that is
Antenna RF Oscillator Key switch I/P and Amplifier
Beacon Controller
FIGURE 14.1 Block diagram of a radio beacon.
DESIGN DESCRIPTION 247
continually executing a program even when the beacon is not transmitting any signal is wasteful. A microcontroller (with power-down features) as the controller can be operated with many of the available power-saving features. AVR processors offer two such power-saving states that reduce power consumption compared to the active state. However, the processor is in some state of inactivity during these power-saving modes and is not executing any program in either of these states. The power-saving modes of operation in the AVR family of processors are called the idle mode and the power-down mode. In the idle mode, the CPU stops executing programs, but the timers, interrupts, and the oscillator keep working. In this mode, an external or an interrupt source of interrupt will wake up the CPU and normal program execution can resume. In the power-down mode of operation, the clock oscillator is also stopped, besides the internal timers and analog comparator. The user can select whether to keep the watchdog timer working. If the watchdog timer is enabled, then the watchdog timer can reset the processor after the watchdog timer expires. Otherwise, only an external reset or an external-level-triggered interrupt can wake up the CPU. The power-down mode of operation reduces the power consumption the most as the internal clock oscillator as well as the timers stop working. In both of these modes of operation, the internal SRAM contents are retained. However, if one chooses the power-down mode of operation and the watchdog timer for wakeup, there has to be some means of keeping a count of the elapsed time. If your particular application needs to do something at a rate that can be met by the watchdog timer, then it poses no problem at all. The watchdog timer has a wakeup range between 15 ms and 2 s. So if your application needs to do something every 2 s approximately, then the watchdog timer could be armed to reset the processor 2 s after it has been enabled and armed. However, what if the application needs a cycle time of 20 s In this case a count of the number of watchdog resets could be maintained in a software counter (in the SRAM), and when this count becomes 10, then the required activity could be performed. However, there has to be some means to distinguish between a power-on reset (or the external reset) and a watchdog reset. There is a complex way to handle this situation. It works on the assumption (and high probability) that the internal SRAM locations would not have a particular sequence of numbers at power on; e.g., the chance of three consecutive SRAM locations at address $00, $01, and $02 to be initialized to say $55, $AA, and $55 respectively is very, very small. In fact, the probability that after power on, these locations will have the exact sequence of numbers is 1/16777216 or about 1 in 100 million. Thus the software could initialize these SRAM locations to the required sequence if after reset these locations are found to contain some other number, thus indicating that the reset was caused by an external reset of a power-on reset and at the same time a software counter in SRAM could be initialized to $00. On the other hand, if the reset has been due to the watchdog timer (and the SRAM locations have been initialized to the required sequence after a power-on reset or an external reset), the SRAM sequence would match and then the software would just examine the software counter, and if the required count has been accumulated in the counter, it would perform the task, reset the counter to $00, enable the watchdog timer once again, and go in to power-down mode. On the other hand, if the software counter has not reached the required count, it will just increment the counter, enable the watchdog timer, and go into power-down mode.
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