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HOW TO BUILD AN ELECTRONIC LOCK 281
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In this chapter, I will show how to build an electronic lock using a scheme that I believe to be quite novel. As I am not aware of the actual lock algorithms that are built into commercial locks, my belief may be more a matter of ignorance than anything else. However, by the end of the chapter you will agree that the scheme I present is indeed an interesting scheme and worth being employed in commercial locks if not already being used. The backbone of the lock scheme that I am going to present is the Linear Feedback Shift Register (LFSR), which we have discussed in a previous chapter. The lock based on LFSR technique exploits the long repeat cycle feature of the LFSR. An 8-bit maximal length LFSR has 255 (28-1) unique combinations. A 20-bit LFSR has a million combinations, and so on. Figure 16.3 shows an 8-bit LFSR of maximal length. The LFSR is operated by first loading a number (called the preset number or the seed) and then shifting this number. Each shift results in a new number that seems to have no relation to the original number. The 8-bit LFSR could be shifted 255 times before the pattern starts repeating. From the point of view of an electronic lock, a bigger shift register would be very useful. By a hacker, it could be seen as transacting random numbers, frustrating any attempts at breaking the lock.
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Seed = 1 2 5 b a1 43 87 42 85 a 55 ab 57 8a 15 2b bf 7e fd bb 77 ee 28 51 a2 8c 19 33 8d 1b 36 5d ba 75 7c f8 f0 d6 ad 5b 13 27 4e 4c 98 30 91 23 47 16 f 14 ae 56 fb dc 44 67 6c eb e1 b6 9d 60 8e 2c 1f 29 5c ac f7 b9 89 ce d8 d7 c3 6d 3b c0 1c 58 3f 53 b8 59 ef 72 12 9c b0 af 86 da 76 81 38 b1 7f a7 70 b3 de e5 25 39 61 5e d b5 ec 3 71 63 ff 4f e0 66 bc ca 4b 73 c2 bd 1a 6a d9 7 e2 c7 fe 9f c1 cc 79 95 96 e7 84 7b 34 d4 b2 e c4 8f fc 3e 83 99 f3 2a 2d cf 8 f6 69 a8 64 1d 88 1e f9 7d 6 32 e6 54 5a 9e 11 ed d3 50 c9 3a 10 3d f2 fa c 65 cd a9 b4 3c 22 db a6 a0 92 74 20 7a e4 f5 18 cb 9b 52 68 78 45 b7 4d 41 24 e9 40 f4 c8 ea 31 97 37 a5 d1 f1 8b 6f 9a 82 49 d2 80 e8 90 d5 62 2f 6e 4a a3 e3 17 df 35 4 93 a4 1 d0 21 aa c5 5f dd 94 46 c6 2e be 6b 9 26 48
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Numbers are in hex.
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FIGURE 16.3 An 8-bit linear feedback shift register with taps at bit positions 1, 2, 3, and 7.
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282 AVR PROJECT 7: SECURITY DONGLE
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The 8-bit LFSR can be increased in length to 16, 20, or more bits to provide more combinations in a real situation. For now, let s build a lock based on this simple 8-bit LFSR. This lock, based on an 8-bit LFSR, is proposed to operate as follows:
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1. The lock is reset every time it is queried. This assures synchronization between the PC
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and the processor in the lock.
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2. The PC sends two bytes of data. The first byte is the seed. 3. The lock calculates the result and returns it back to the PC. 4. The PC also calculates the result and compares it with the result sent by the lock. When
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both of them match, the PC concludes that a valid lock is present and then continues executing the application software. The data transfer between the PC and the lock is serial data transfer with Strobe and Ack handshake signals. The parallel port has three ports, as we have seen in a previous chapter. We use the D0 (DATA port bit0) signal from the parallel port to output serial data from the PC to the lock, the S7 (STATUS port bit7) signal to receive serial data from the lock, the D1 (DATA port bit1) signal from the PC as Strobe to the lock, and S6 (STATUS port bit6) as Ack from the lock to the PC. On the lock side, we use PB0 for serial data input and output, PB1 as Strobe input, and PB2 as Ack output to the PC. Another signal D2 (DATA port bit D2) is used to reset the processor. Figure 16.4 illustrates the block diagram of our scheme. You may note that signal PB0 from the processor is connected to D0 as well as S7 signal pins of the parallel port. These connections cannot be made as it is; we have to isolate the D0 signal pin from the S7 signal pin so that when PB0 is sending data out to S7, the logic level on D0 does not affect the logic levels being set up by PB0.
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