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25 pin D type Male Connector
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AT90S2343 (or Tiny22) D0 S7 D1 S6 D2 PB0 PB0 PB1 PB2 RESET
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FIGURE 16.4 Block diagram of the lock and the PC parallel port signal configuration.
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HOW TO BUILD AN ELECTRONIC LOCK 283
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To achieve this isolation, we use a 1-input AND gate as illustrated in Figure 16.5. The AND gate input is connected to D0 and the output is connected to PB0 as well as S7. Thus when the input of the AND gate is 1 , the diode is cut off and the logic level on D0 is isolated from the logic levels being set up by PB0. Figure 16.6 illustrates the effect of using a passive gate like the 1-input AND gate on logic levels. When the input to the gate is 0 , the diode conducts and the output voltage is the input voltage the forward voltage drop on the diode. If the input 0 voltage is 0.5 V (a valid TTL compatible logic 0 ) and we use a silicon diode with a forward drop of 0.6 volts, the output voltage would be 1.2 V which is not a valid TTL level 0 . In Figure , 16.6, we have used a germanium diode (forward voltage drop 100 300 mV), and the voltage shift on the output signal is about 200 mV which is a valid logic 0 TTL signal. Figure , 16.6 illustrates the hidden dangers of using discrete passive logic and its potential to alter signal levels.
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FIGURE 16.5 A 1-input AND gate used as a level isolation circuit.
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About 200 mV of level shift on logic 0
output of the 1-input diode AND gate
Square wave generated on D0 (pin2) of the parallel port applied to the 1-input diode AND gate
FIGURE 16.6 The effect of driving a 1-input diode AND gate with a logic signal.
284 AVR PROJECT 7: SECURITY DONGLE
16.4 Design Description
Now that we have seen the plan for our version of the electronic lock, it is time to dive into the actual circuit. Figure 16.7 is the circuit schematic for the security lock. The circuit shows a Tiny22 processor, but an AT90S2343 processor with its internal RC clock circuit enabled would do just as well. Let s plod through the circuit. Connector J1-1 and J1-2 are used to apply power ( 5 V) to the circuit. For a real lock, this power would be derived out of the port to which it gets connected. Capacitors C5 and C6 are used to filter the incoming supply voltage. IC U1 is a Tiny22 processor, and I have also tested the circuit with an AT90S2343 processor with its internal RC oscillator enabled. Either of these processor could be used. Connector J2 is the parallel port DB-25 male connector. This connector mates to the parallel port DB-25 female connector on the PC. Resistor R2 is connected to pin J2-4 (DATA port signal D2), which resets the processor by applying logic 0. Since we have used capacitor C4 on the reset pin of the processor to filter any unwanted noise, R2 limits the discharge current from C4 to damage the port bit D2 of the parallel port. A charged capacitor can discharge large currents (limited by the load resistor), and to limit this current, we have used R2 (470 ohm). The resulting discharge current (about 10 mA, worst case) can easily be handled by the parallel port pin. To reset the processor, the D2 signal is taken to logic 0 for a small time (.001 s) and them taken to 1. This resets the processor. Pin J2-11 of the parallel port S7 (STATUS port signal bit7) is connected directly to the PB0 bit of the processor and is used to receive serial data transmitted by the processor to the PC. Pin J2-2 of the parallel port is the D0 (DATA port bit D0) signal pin and is connected to the PB0 pin through diode D1. Diode D1 and resistor R1 form the 1-input diode AND gate that we have already discussed. When the PC wants to receive data from the processor, it first puts signal D0 to 1 and then triggers the processor to send data. Pin J2-3 is signal D1 (DATA port bit1) of the parallel port and is an output pin from the parallel port used as a Strobe signal by the PC. It is connected to pin PB1 of the processor. Finally, pin J2-10 is signal S6 (STATUS port bit6) and is an input pin of the parallel port used to receive the Ack signal from pin PB2 of the processor.
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