barcode reader in asp.net FIGURE 16.7 Circuit schematic for the PC parallel-port-based security lock using AT90S2343. in Software

Maker Code 128A in Software FIGURE 16.7 Circuit schematic for the PC parallel-port-based security lock using AT90S2343.

FIGURE 16.7 Circuit schematic for the PC parallel-port-based security lock using AT90S2343.
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Let us see how this circuit is able to exchange data. The circuit is set up to transmit data in chunks of 8 bits, 1 bit at a time, i.e., serially. This data transfer between the PC and processor is synchronous, and the Strobe signal acts like a clock when the data is transferred from the PC to the processor, while when the processor transmits data to the PC, the Ack signal acts like the synchronizing clock. Any data transfer scheme between two devices must ensure that data is always exchanged without any loss. To ensure that, some kind of handshake signals are used. We call these signals Strobe and Acknowledge. Figure 16.8 shows how these signals are used to exchange data between a master device and a slave device. One of the devices is called the master, as it initiates all transfers. The other is called slave, as it always obeys the master. Figure 16.8 shows a data bus, however this scheme is true for exchanging even a single bit of data between the master and the slave, as is our case. This scheme is also used by the master to receive data from the slave. In this mode, to receive data, the master checks that the master has de-asserted the Ack signal, and after that asserts the Strobe signal. The slave responds by placing the data on the data line and then asserting the Ack signal. The asserted level on the Ack line signals the master that data is available for it to read. The master reads the data and then lowers (de-asserts) the strobe signal. When the slave sees the de-asserted signal level on the Strobe line, it knows that the master has received the data and so it can lower its own Ack signal. This completes one cycle of data transfer between the master and the slave. I captured the Strobe and the Ack signal activity on a digital oscilloscope, and this is illustrated in Figure 16.9. The Strobe signal is always activated only when the Ack signal is 0 and the Strobe signal goes low after the Ack signal is at logic 1.
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Start of Data transfer Cycle 7. Master sees in-active 1. Master checks Ack deasserted 5. Master sees asserted Ack Ack . puts new data if means that data has been read 2. Master puts data on data lines required, for a fresh data deasserts Strobe 3. Master asserts Strobe transfer cycle Data transfer cycle ends
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Strobe
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4. Slave sees active Strobe . Asserts Ack .
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6. Slave processes the data. and when ready for more, deasserts Ack .
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FIGURE 16.8 Data transfer between a master and a slave using strobe and Ack handshake lines.
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286 AVR PROJECT 7: SECURITY DONGLE
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PC Strobe
Controller Ack
FIGURE 16.9 Scope trace illustrates the time relationship between the Strobe generated by the PC as the master and the Ack by the AT90S2343 as a slave.
Another scope trace is illustrated in Figure 16.10 with data input and output signals (i.e., signals on the PB0 pin) and the PC Strobe. This particular trace was obtained by programming the PC and the processor to transmit a data byte from the PC and immediately receive the transmitted data from the processor. The trace illustrates the effect of the diode AND gate in the form of a 1.2-V level shift on the logic 0 signal transmitted from the PC. However, this does not seem to be a problem for the processor, as it seems to get the correct data and transmit it back as sent from the latter half of the data trace. This latter half of the data signal is from the processor to the PC (received by the PC on the S7 signal pin J2-11). What happens if the processor does not deassert the Ack signal In our scheme the PC must wait till the Ack signal is deasserted by the processor, and this is what exactly happens. I captured the trace of the Strobe and Ack signal between the PC and processor after the PC and the processor code was completed as required for this lock application. Figure 16.11 illustrates the trace. The PC transmits 2 bytes to the processor as we have discussed; the processor then calculates the result, and this could take time, depending upon the value fo the second byte that the PC transmits. During this time the processor holds the Ack signal asserted, thus signaling to the PC that the processor is not yet ready to complete the transaction. The PC waits till the Ack signal is lowered and then proceeds with receiving the result byte from the processor.
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