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FIGURE 17.2 Frequency counter timing diagram.
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294 AVR PROJECT 8: A PULSE FREQUENCY COUNTER WITH AN RS-232 INTERFACE
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Input Amplifier and Wave Shaper
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Gate Control Controlled Gate Counter Chain Display or Transmitter
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Time-base generator and Control Circuit
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FIGURE 17.3 A period counter.
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Input Signal
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Gate Control Signal
Time-Base Output Output of the Gate
FIGURE 17.4 A period counter timing diagram.
is the associated timing diagram. As illustrated from the block diagrams for the frequency counter as well as the period counter, such a device would need many ICs for implementing the various functions. Such a device could be easily implemented using a microcontroller for reducing the component count as well as for providing many additional functions of data manipulation. An AVR processor is capable of implementing a dual period/frequency counter function with a minimum of components, as illustrated in Figure 17.5. The AVR ports are capable of driving LED displays directly; also, internal timers could be used for the time-base generation and counting functions. All that would be required would be an external amplifier that would provide digital, TTL compatible signal to the AVR. The figure illustrates some switches connected to the AVR for selcting time-base frequency or mode, etc. Besides, the built-in serial port of the AVR provides additional connectivity to a PC for remote control of the instrument or for downloading data for further manipulation or analysis. The next section discusses the design of a very compact AVR-processor-based frequency counter. The design is expandable to include more features as desired.
DESIGN DESCRIPTION OF AN AVR-PROCESSOR-BASED FREQUENCY COUNTER 295
Power Supply Counter Display Amplifier and Wave Shaper AVR Processor RxD TxD Gnd PC Serial Port (RS-232)
Mode Selection Switches
FIGURE 17.5 A compact multifunction period/frequency counter.
17.5 Design Description of an AVRProcessor-Based Frequency Counter
This section discusses an AT90S2323-processor-based frequency counter with selectable gate period. The selected processor has just enough I/O lines to permit use as a frequency counter; in fact, all the three I/O lines of the processors are used in this design. Figure 17.6 illustrates the block diagram of the frequency counter. The features of this frequency counter are: Accepts TTL-level digital signals whose frequency is to be measured. User interface is provided through a PC RS-232 serial port. A choice of three gate pulse periods: 0.1s, 1s, and 10s. Does not require an external power supply. The circuit derives the required power from the RS-232 port of the PC. 5. Uses only a handful of components.
1. 2. 3. 4.
The objective for this design was to build a frequency counter that was very small in size and could count the frequency of digital signals of frequency up to 10 KHz and with different gating periods as listed above. Another objective was to avoid using an external power supply, thus the choice to use the RS-232 port to draw power was a good choice. However, it also meant that the circuit should be low power and should manage in a few milliamps of current, which is usually available from an RS-232 port. From the large selection of the AVR processors, many processors could meet this design objective. Ideally, I would have liked to use an AT90S2343 and use the internal 1-MHz RC oscillator so as to minimize component count. However, it was found that the internal RC oscillator frequency has a large dependence on the supply voltage, and since the supply voltage for the project was to be derived from the
296 AVR PROJECT 8: A PULSE FREQUENCY COUNTER WITH AN RS-232 INTERFACE
Power Supply
RxD PC Serial Input Pulses AT90S2323 (TTL Level) Gnd TxD Port (RS-232)
3.58 MHz
FIGURE 17.6 An AVR-based frequency counter with an RS-232 interface.
RS-232 port and hence expected to be not so stable, this did not seem a feasible processor to use. I then decided to use the AT90S2323, which is very much like the AT90S2343 except that it requires an external crystal. The AT90S2323 has 128 bytes of internal SRAM but no built-in UART (serial port). So it was decided to create a software-driven serial port. Figure 17.7 illustrates the circuit schematic for the frequency counter. The power to the circuit is derived out of the RTS signal of the PC RS-232 port. Diode D1, resistor R2, and zener Z1 generate the required supply voltage. The diode is 1N4148 signal diode and is used to ensure that only positive voltage is applied to the circuit. Zener Z1 is selected to be 5.1 V and R2 is 470 ohm to limit the current into the zener diode. Capacitors C5 and , C6 are used as supply filter capacitors. The circuit is operated with a 3.58-MHz crystal. Any other crystal could also be used. In fact, a smaller-value crystal would lead to reduced current consumption by the circuit, however it would also restrict the range of input signal frequency that can be measured by the frequency counter as well as the minimum pulse width of the signal frequency. Pin PB0 of the processor is connected to the TxD signal pin of the RS-232 port (Figure 17.8). Pin PB0 is programmed as an input pin. Diodes D2, D3, and resistor R3 are used to clamp the positive swing of the TxD signal to within the supply voltage of the processor. When the TxD signal is -ve, the diode D3 blocks it and the resistor offers a logic low to the PB0 pin. The effect of D2, D3, and R3 in restricting the incoming bipolar RS-232 signal to a clamped and rectified TTL signal is illustrated in the oscilloscope trace in Figure 17.9. Pin PB1 of the processor is programmed as an output pin, and this pin drives the RxD signal pin of the RS-232 port. Please note here that the processor is not generating legal RS-232 voltage swings. However, 0 volts to an RS-232 input is taken as a marking signal and I found that the circuit worked without any problems on a variety of PC machines. The PB1 pin swings between 0 volts on one end and the supply voltage on the other.
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