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In the 1940s, the United States government asked Harvard and Princeton Universities to come up with a computer architecture to be used in computing tables of naval artillery shell distances for varying elevations and environmental conditions. Princeton s response was for a computer that had common memory for storing the control program as well as variables and other data structures. It was best known by the chief scientist s name, John Von Neumann. Fig. 1.4 is a block diagram of the architecture. In contrast, Harvard s response was a design (shown in Fig. 1.5) that used separate memory banks for program storage, the processor stack, and variable RAM. The Princeton architecture won the competition because it was better suited to the technology of the time; a single
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Figure 1.4 Princeton computer architecture block diagram.
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Figure 1.5 Harvard computer architecture block diagram.
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memory space was preferable because of the unreliability of the current electronics (this was before transistors were even invented) and the simpler interface would have fewer parts that could fail. The Princeton architecture s memory interface unit is responsible for arbitrating access to the memory space between reading instructions and passing data back and forth to the processor. This hardware is something of a bottleneck between the processor s instruction processing hardware and the memory accessing hardware. In many Princeton-architected processors, the delay is reduced because much of the time required to execute an instruction is normally used to fetch the next instruction (this is known as pre-fetching). Other processors (most notably the Pentium processor in your PC) have separate program and data caches that pass data directly to the appropriate area of the processor while external memory accesses are taking place. The Harvard architecture was largely ignored until the late 1970s when microcontroller manufacturers realized that the architecture did not have the instruction/data bottleneck of the Princeton architecture based computers. The dual data paths give Harvard architecture computers the ability to execute instructions in fewer instruction cycles than the Princeton architecture due to the instruction parallelism possible in the Harvard architecture. Parallelism means that instruction fetches can take place during previous instruction execution and not wait for either a dead cycle of the instruction s execution or have to stop the processor s operation while the next instruction is being fetched. After reading this description of how data is transferred in the two architectures, you probably feel that a Harvard-architected microcontroller is the only way to go. But the Harvard architecture lacks the exibility of the Princeton in the software required for some applications that are typically found in high-end systems such as servers and workstations. The Harvard architecture is really best for processors that do not process large amounts of memory from different sources (which is what the Von Neumann architecture is best at) and have to access this small amount of memory very quickly. This feature of the Harvard architecture (used in the PIC microcontroller s processor) makes it well suited for microcontroller applications.
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Once the processor s architecture has been decided upon, the design of the architecture goes to the engineers responsible for implementing the design in silicon. Most of these details are left under the covers and do not affect how the application designer interfaces with the application. There is one detail that can have a big effect on how applications execute and that is whether the processor is a hardwired or microcoded device. The decision between the two types of processor implementations can have signi cant implications as to the ease of design of the processor, when it is available, and its ability to catch and x mistakes. Each processor instruction is in fact a series of instructions that are executed to carry out the larger, basic instruction. For example, to load the accumulator in a processor, the following steps need to be taken: Output address in instruction to the data memory address bus drivers. Con gure internal bus for data memory value to be stored in accumulator. Enable bus read. Compare data values read from memory to zero or any other important conditions and set bits in the STATUS register. 5 Disable bus read.
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Each of these steps must be executed in order to carry out the basic instruction s function. To execute these steps, the processor is designed to either fetch this series of instructions from a memory or execute a set of logic functions unique to the instruction. A microcoded processor is really a processor within a processor. In a microcoded processor, a state machine executes each instruction as the address to a subroutine of instructions. When an instruction is loaded into the instruction holding register, certain bits of the instruction are used to point to the start of the instruction routine (or microcode) and the Code instruction decode and processor logic executes the microcode instructions until an instruction end is encountered as shown in Fig. 1.6.
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