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Mainline Jump to 0x00004 0x00004 retfie Mainline +1
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Interrupt Request Interrupt Request Flag ( F ) GIE Mainline Executing/ Interrupt Request Received Interrupt Acknowledged Interrupt Handler Executing Interrupt Request Handled/ Resume Mainline
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Figure 6.19 request.
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Mid-range PIC microcontroller response to an interrupt
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PIC microcontroller, two cycles are required to ush the prefetch buffer and to load in the next instruction before it can be executed. Along with looking at the two-instruction cycle operation of the execution changes, note that the jump to the interrupt vector cannot take place until the current instruction has nished executing. This is important because it means that the timing for the interrupt handler is not 100 percent predictable. The operation of the interrupt handler will lengthen by one instruction cycle if a call, jump, or PCL update is taking place when the interrupt request comes in. In these cases, the jump to the interrupt handler will have to wait for the two-cycle instruction to complete before the jump can take place, and this results in a maximum four-instruction-cycle interrupt latency instead of the bestcase situation of three-instruction-cycle latency. I am mentioning this because where you are most likely to see a difference in the response to an interrupt request is in the MPLAB simulator, where the jump to the interrupt handler may happen one cycle later than you expect. Not expecting this can cause you to look through the code, trying to nd the reason for this anomaly. There are very few cases where the one-instruction-cycle delay will be a problem, but when you are rst working with the PIC microcontroller, this can cause you some confusion. If you forget to reset the F ag, or if another interrupt event requests the interrupt handler before the current request has completed, you will nd that execution will not seem to return to the mainline. Instead, immediately following the ret e instruction, the rst instruction of the interrupt handler (at address 0x0004) will be executed. You can starve the mainline code of cycles if interrupt requests come in continuously before the handler returns to the mainline code or if the interrupt request ags are not reset. Starving the mainline of instruction cycles owing to interrupt operation is something that is very hard to nd when you are debugging your application. In fact, I would consider it to be one of the hardest problems to nd for someone new to the PIC microcontroller because the simulator probably will not show what happens with the volume of requests (especially if they come from peripherals).
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The four different PIC microcontroller architectures have a number of similarities, and many of their differences are more a result of the instruction word sizes than of features added or deleted in the processor itself. The mid-range PIC microcontroller architecture is the most popular at the time of this writing because of the number of packages and pin con gurations, as well as the variety of peripherals available. The low-end architecture has the basic features of the mid-range architecture, although it does not have the peripheral options and interrupt capabilities. The high-end architecture is represented by the PIC18, with more memory, a more sophisticated processor, and peripherals. The PIC17 architecture is an older architecture that did not gain wide acceptance, and there are no plans by Microchip to develop new part numbers for it; the PIC17 is not recommended as a platform for new applications. As I will point out elsewhere in
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THE MICROCHIP PIC MCU PROCESSOR ARCHITECTURE
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this book, I have focused on the mid-range PIC microcontroller processor architecture because it has the most commonality with the other architectures. The primary differences you must understand before working with different PIC microcontroller architectures are
1 Program counter circuitry 2 Register organization
So far in this chapter I have focused exclusively on the mid-range PIC microcontroller architecture and how it operates. For the remainder of this chapter I will discuss the differences in the architectures of the low-end and PIC18 microcontrollers. The PIC17 architecture is also discussed brie y.
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