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The low-end PIC microcontroller devices have a very similar architecture to that of the mid-range devices, although it is missing some of the features of mid-range devices. The most obvious omission is lack of the addlw and sublw instructions, but there are some other, subtler differences as well that you will have to deal with. One of these differences is a change in the reset vector compared with mid-range PIC microcontrollers. In the mid-range devices, reset is always 0, but in low-end devices, this address is always the last address in program memory. Table 6.6 lists the reset vector addresses for different low-end devices program memory sizes. I recommend ignoring the reset vector address and instead treating the reset vector address as address 0, which will be the next instruction executed after the instruction at the real reset vector and the processor s program counter rolls over and continues from 0. If the instruction is left unprogrammed, then it will be executed as the instruction xorlw 0xFF, which essentially negates the initial contents of the w register which are unknown because the value in the w register is unde ned at power-up, as are all the other le registers. By ignoring the last instruction, you are allowing applications to be written very similarly to mid-range applications and not have any differences in regard to reset. It is important to remember that this last address must be left unprogrammed with no instructions placed in it.
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TABLE 6.6 LOW-END PIC MICROCONTROLLER PROGRAM MEMORY SIZE TO RESET VECTOR ADDRESS PROGRAM MEMORY SIZE RESET VECTOR
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512 instructions 1024 instructions 2048 instructions
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In the following two sections I will describe the differences in the program counter hardware and the register addressing hardware between low-end and mid-range devices. These are the major differences between the two architectures (along with the availability of interrupts in the mid-range). Later in this book I will discuss strategies for writing applications in such a way that moving code and full applications between the two architectures is relatively simple. I consider the register organization of the low-end PIC microcontrollers to be the largest differentiator between them and the mid-range devices. The use of a 32-bit bank with no bank select bits considerably reduces the possible number of le registers and the usability of (relatively) large tables in low-end PIC microcontrollers. While I am disappointed by how few le registers are available and the dif culty in accessing what is available, I do think that low-end PIC microcontroller s are usable and should be considered when specifying which PIC microcontroller to use in an application. The low-end register space is shown in Fig. 6.20. The low-end PIC microcontroller s TRIS and OPTION registers can be written to only using the tris and option instructions. These instructions are explained in detail in 7, but note that I write them in lower case this is done to differentiate them from the TRIS and OPTION registers, which are denoted by writing the register labels in upper case. Low-end instructions only provide 5 bits for a register address in a direct-addressing instruction and take the form
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Bank 0 Addr - Reg 00 - INDF 01 - TMR0 02 - PCL 03 - STATUS 04 - FSR 05 - PORTA* 06 - PORTB 07 - PORTC 08-0F Shared File Regs 10-1F Bank 0 File Regs
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Bank 1 Addr - Reg 20 - INDF 21 - TMR0 22 - PCL 23 - STATUS 24 - FSR 25 - PORTA* 26 - PORTB 27 - PORTC 28-2F Shared File Regs 30-3F Bank 1 File Regs
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Bank 2 Addr - Reg 40 - INDF 41 - TMR0 42 - PCL 43 - STATUS 44 - FSR 45 - PORTA* 46 - PORTB 47 - PORTC 28-2F Shared File Regs 50-4F Bank 2 File Regs
Bank 3 Addr - Reg 60 - INDF 61 - TMR0 62 - PCL 63 - STATUS 64 - FSR 65 - PORTA* 66 - PORTB 67 - PORTC 68-8F Shared File Regs 70-7F Bank 3 File Regs
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