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Bank Unique Registers
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* - OSCCAL may take place of PORTA in PICMicros with Internal Oscillators
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OPTION - Accessed via option Instruction TRIS# - Accessed via TRIS PORT# Instruction
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Figure 6.20 The low-end PIC microcontroller architecture has I/O registers at the same position within each bank as well as a common le register area.
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THE MICROCHIP PIC MCU PROCESSOR ARCHITECTURE
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where INSTRT is the bit pattern for the instruction, d is the destination (1 stores the result back in the register, and 0 stores the result in the w register), and RRRRR is the register address. In these direct-addressing instructions, only the registers in the rst bank can be accessed. Accessing registers in other banks requires use of the FSR register. As can be seen in Fig. 6.20, the rst 16 addresses of each bank are common. The 16 bank-unique le registers are located in all the last 16 addresses of the bank. This limitation of only being able to address data 16 bytes at a time prevents the construction of arrays or other data structures that are longer than 16 bytes. Of course, you could work out an algorithm for changing the FSR s high-order bits (bits 5 and 6) to simulate an array of greater than 16 bytes, but rather than doing this, I would recommend that you go to one of the other PIC microcontroller architectures for the application instead. There can be up to four banks in low-end devices. If 16 le register bytes are available in the last half of each bank and 8 or 9 le registers are available in the rst half (depending on whether or not port C is available), the maximum number of unique le registers in the low-end PIC microcontroller is 72 or 73. One quirk that I should point out is that the low-end PIC microcontroller s FSR register can never equal 0. Instead of ignoring unused high-order FSR bits, Microchip s designers instead elected to set them. Even if all four bank registers are used for a total of 128 FSR accessible registers, the FSR register cannot be equal to 0; the FSR register bit 7 will be set. Table 6.7 lists which bits will be set in the low-end s FSR depending on how many bank registers the PIC microcontroller has. It can be hard to remember that the low-end s FSR register can never be 0. Chances are that you ll only remember it after you ve tested the contents of FSR with an instruction sequence such as
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movlw xorwf 0 FSR, w
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and discovered that the result never returns 0. If you check the contents of the FSR in applications such as stacks, arrays, and circular buffers, but if you try to implement the set-bit boundaries as a way of avoiding having to check or reset bits in the FSR, then you may discover that the code is not very portable either to mid-range PIC microcontroller devices or to other low-end parts that may have fewer or more le registers, which affects the number of banks and which bits of the FSR are set.
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TABLE 6.7 LOW-END PIC MICROCONTROLLER MINIMUM FSR VALUE TO NUMBER OF BANKS NUMBER OF BANKS SET FSR BITS MINIMUM FSR VALUE
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1 2 4
7, 6, 5 7, 6 7
0xE0 0xC0 0x80
ARCHITECTURE DIFFERENCES
Program counter The low-end PIC microcontroller s program counter is quite a bit different from that of the mid-range PIC microcontroller. If you look at the standard register set for the low-end device, you ll see that there is no PCLATH register, and the pageselect bits are part of the STATUS register (where the bank-select bits are in the mid-range PIC microcontroller). In addition, owing to limitations in the low-end architecture, there are some problems with being able to place and work with tables and subroutines that you should be aware of. The differences between the low-end PIC microcontroller s program counter and that of the mid-range device are partially based on the 512 instruction page size of the low-end PIC microcontroller (the mid-range has a 2,048 instruction page size). In low-end devices, execution stays within these 512 instructions unless an interpage jump on call is executed or execution simply passes from a lower page to an upper page. The low-end PIC microcontroller s program counter block diagram is shown in Fig. 6.21. The PA0 and PA1 bits of the STATUS register (bits 5 and 6) perform the same function as the PCLATH register of the mid-range PIC microcontrollers. Bit PA0 is used to provide bit 9 of the destination address to jump to during a goto or call instruction or when PCL is written to. Bit PA1 is address bit 10. In some low-end PIC microcontrollers, you will see bit 7 of the STATUS register being referred to as PA2. This bit is not used for addressing in any of the low-end PIC microcontrollers available at the time of this writing. In mid-range devices, to perform a jump based on changing PCL, the following code is used: PCLATH = HIGH new_address; PCL = LOW new_address;
In low-end PIC microcontrollers, this operation is quite a bit more complex because while the PA0 through PA2 bits are updated, none of the other bits in the STATUS register
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