PIC17Cxx ARCHITECTURE in Software

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PIC17Cxx ARCHITECTURE
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The PIC17 architecture was developed originally before the mid-range architecture as one that could be used for advanced applications. The architecture met with limited success and has not been proliferated like the other three architectures. There are much more signi cant architecture differences between the PIC17 and the mid-range parts than differences between the mid-range and low-end and PIC18 architectures. The unique features of the PIC17Cxx compared with the other PIC microcontroller s include
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The ability to access external, parallel memory Up to seven I/O ports A built-in 8 8 multiplier Up to 902 le registers in up to 16 banks Up to 64 kB of address space The ability to read and write program memory Multiple interrupt vectors
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Along with these enhanced features, block diagrams of the PIC17, such as Fig. 6.22, further make you feel like the PIC17Cxx is unique and not that portable between the other PIC microcontroller architectures. The important differences in the PIC17 architecture are
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1 The STATUS and OPTION_REG register functions are spread across different
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registers.
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2 The program counter works slightly differently from the other architectures. 3 The registers are accessed differently, and accesses can bypass the WREG.
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THE MICROCHIP PIC MCU PROCESSOR ARCHITECTURE
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PIC17 processor and register architecture.
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Interrupts in the PIC17 are similar in operation to those in the mid-range PIC microcontroller, with an E bit enabling the interrupt request ag bit (the F bit) to request that the processor execute the appropriate interrupt handler. The PIC17 does not have a GIE bit that enables interrupts but does have the GLINTD bit, which must be reset for interrupt requests to be passed to the processor I like to think of it as the _GIE (negative GIE) bit.
ARCHITECTURE DIFFERENCES
TABLE 6.8 PIC17 INTERRUPT VECTOR ADDRESS AND PRIORITIES FOR DIFFERENT INTERRUPT REQUEST SOURCES PRIORITY VECTOR ADDRESS SOURCE
High
0x08 0x10 0x18
RA0/INT pin interrupt request TMR0 over ow interrupt request TOCKI pin interrupt request Peripheral device interrupt request
0x20
Depending on which interrupt is requested and acknowledged, execution will jump to a different interrupt vector address. If multiple interrupts are requested at the same time, the highest priority one will be serviced rst. The interrupts, their priorities, and their vectors are listed in Table 6.8. The PIC17Cxx s register space is designed around a single 8-bit register address built into the instruction set. Like the low-end and mid-range PIC microcontrollers, the PIC17Cxx uses multiple register banks to allow the user to access more registers than just this base number. Unlike the low-end and mid-range PIC microcontrollers, there are two bank areas to access registers, and each one has its own set of address bits. I normally think of the PIC17Cxx s registers as being organized like Fig. 6.23.
Address
0x000 INDF0 FSR0 PCL PCLATH ALUSTA T0STA CPUSTA INTSTA INDF1 FSR1 WREG TMR0L TMR0H TBLPTRL TBLPTRH BSR
Primary ("P") Registers File ("F") Registers
0x00F 0x010 0x017 0x018 0x019 0x01A 0x01F 0x020 0x0FF
Special Function Registers
PRODL PRODH
BSR3-BSR0 Select Special Special Function Function Registers Registers
File Registers
BSR7-BSR4 Select
File Registers File Registers
File Registers
Figure 6.23 PIC17 register organization showing multiple register blocks.
THE MICROCHIP PIC MCU PROCESSOR ARCHITECTURE
The rst 32 register addresses (0x000 to 0x0IF) are known as the primary register set. These registers are the primary processor and PIC microcontroller hardware features. The hardware interface registers are the special function registers (SFR) located at the register banks in 0x010 to 0x0iF with up to 16 banks. The P register special function register banks are selected by the least signi cant 4 bits of the bank select register (BSR), as I ve shown in Fig. 6.23. The 5 address bits of the primary register set and the 8 of the full register set allow data to be moved quickly and easily within the register space without having to go through the WREG. For example, moving the contents of 0x042 and 0x043 to the TMR0L and TMR0H registers could be accomplished by using the movfp instructions, which pass data from the f (full) register set to the primary:
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