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TABLE 6.9
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PIC18 FSR CHANGE ACCESS REGISTERS OPERATION
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INDF REGISTER
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INDF# POSTINC# POSTDEC# PREINC# PLUSW#
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Access the register pointed to by FSR# Access the register pointed to by FSR# and then increment FSR# Access the register pointed to by FSR# and then decrement FSR# Increment FSR# and then access the register pointed to by FSR# Access the register pointed to by the contents of the WREG added to FSR#
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THE MICROCHIP PIC MCU PROCESSOR ARCHITECTURE
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When I discuss compilers later in this book, I discuss the operations carried out based on the traditional PIC microcontroller architectures. The capabilities of the FSR register in the PIC18 allow the FSR registers to simulate stack operations. For example, to simulate a push of the contents of the WREG using FSR0 as a stack pointer, the operation
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POSTDEC0 = WREG;
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could be used. Going the other way, a pop WREG could be implemented as
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WREG = PREINC0;
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In the rst case, the stack is decremented after a data value is placed on it. When the data value is to be popped off, the stack pointer (FSR0) is incremented, and the data value it is pointing to is returned. I speci ed this order of operations to allow access to pushed stack items. Each time a value is pushed, the FSR register is decremented. To go back and access other items, I can use the PLUSW0 register to read a stack element. For example, to read the element placed three pushes earlier, I would use the code
WREG = 3; WREG = PLUSW0;
This example, while showing how the FSR access with offset works, does not take into account the abilities of the PIC18 instruction set. Using the preceding example as a basis, you probably would assume that writing into the FSR stack at a speci c offset is not simple. This is so because there is no way to add a constant from the WREG and have a value somewhere that can be accessed and written by the FSR register. The PIC18 s movff instruction allows data transfers using an FSR index register and the WREG offset without accessing WREG in any way. The PIC18 s program counter and its stack are similar in operation to those of the other PIC microcontrollers, but they have the ability to be modi ed under application software control. This new capability greatly enhances the PIC18 s ability to run multitasking operating systems or monitor programs compared with the other PIC microcontrollers. This is an exciting feature and one that I will take advantage of later in this book. The PIC18Cxx program counter and stack are similar to the hardware used in the other PIC microcontroller architectures except for three important differences. The rst difference is the additional bits required for a program counter accessing 20 address bits for the maximum 1 million possible instructions of program memory. The second difference is the availability of the fast stack, which allows interrupt context register saves and restores to take place without requiring any special code. The last difference is the ability to read and write from the stack. These differences add a lot of capabilities to the PIC18 that allow applications that are not possible in the other PIC microcontroller architectures. In the PIC18, when handling addresses outside the current program counter, not only is a PCLATH register (or PA bits as in the low-end devices) update required, but also a highorder register update for addresses above the rst 64 instruction words. This register is known as PCLATU. PCLATU works identically to the PCLATH register, and its contents are loaded into the PIC18Cxx PIC microcontrollers program counter when PCL is updated.
Program counter
ARCHITECTURE DIFFERENCES
Each instruction in the PIC18 starts on an even address. This means that the rst instruction starts at address 0, the second at address 2, the third at address 4, and so on. Setting the program counter to an odd address will result in the MPLAB simulator halting and the PIC18 working unpredictably. Changing the convention used in the previous PIC microcontrollers to one where each byte is addressed means that some rules about addressing will have to be relearned for the PIC18. The fast stack is an interesting feature that will simplify your subroutine calls (in applications that don t have interrupts enabled), as well as working with interrupt handlers. To use the fast stack in the call and return instructions, a 1 parameter is put at the end of the instructions. To prevent the fast stack from being used, a 0 parameter is put at the end of the call and return instructions. The fast stack is a 3-byte memory location where the w, STATUS, and BSR registers are stored automatically when an interrupt request is acknowledged and execution jumps to the interrupt vector. If interrupts are not used in an application, then these registers can be saved or restored with a call and return such as
call sub, 1 STATUS ; and BSR : Sub: STATUS : return 1 before ; Return to Caller ; Call sub after saving w ,
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