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THE MICROCHIP PIC MCU PROCESSOR ARCHITECTURE
Program Counter Stack Element 0 Element 1 Element 2 TOSU TOSH 21 Bits TOSL
StkPtr 5 Bits
Element 30 20 Bits
Figure 6.27 The data on the PIC18 stack is accessible from the program using the TOS# registers.
Note that in the interrupt handler, the w register is restored before the STATUS register so that the status ags are not changed by the movf instruction after they have been restored. This code should be kept in your hip pocket until it is required. The last difference is also the most signi cant. The ability to access the stack is quite profound, and a deeper understanding of the PIC18 s stack is required than for the other PIC microcontroller processor architectures. The stack itself, at 31 entries, is deeper than the other PIC microcontroller stacks, and the hardware monitoring the stack is available as the STKPTR register. A block diagram of the stack is shown in Fig. 6.27, whereas the STKPTR register bit de nitions can be found in Table 6.10. The STKUNF and STKFUL bits will be set if their respective conditions are met. If the STVREN bit of the con guration fuses is set, then when the STKUNF and STKFUL conditions are true, the PIC microcontroller will be reset. I m of a mixed mind as to the appropriateness of resetting the PIC microcontroller after an invalid stack operation. While a reset de nitely will indicate that an error has occurred (just like a watchdog timer timeout), there would be a problem with decoding what has happened. Ideally, there would be an interrupt that could have its own handler to report and deal with the issue. The value at the top of the stack can be read (or written) using the top or stack (TOSU, TOSH, and TOSL) registers. These registers are pseudoregisters like INDF.
TABLE 6.10 BIT
PIC18 STKPTR REGISTER BIT DEFINITIONS
DESCRIPTION
7 6 5 4-0
STKFUL stack full ag, which is set when the stack is full or over owed STKUNF stack under ow ag, which is set when more stack elements have been popped than pushed Unused SP4:SP0 stack pointer
ARCHITECTURE DIFFERENCES
These registers access the top of the stack directly. When an address is pushed onto the stack, the SP bits of the STKPTR register are incremented, and then the TOSU, TOSH, and TOSL registers are updated. Address pops happen in the reverse order; data is taken out of the TOSU, TOSH, and TOSL registers, and then the stack pointer bits are decremented. The PIC18 has push and pop instructions that increment and decrement the stack pointer and SP bits. These instructions should be used for changing the stack pointer, and the SP bits never should be written to directly to avoid any possible damage to the stack and being unable to return to the caller. Using the TOS registers, the stack can be recorded or changed. For example, if you want to implement a computed return statement, the following computational algorithm could be used:
TOSU = ((TableStart & 0x0FF0000) >> 8) ((offset & 0x0FF0000) >> 8); if ((((TableStart & 0x0FF00) >> 4) ((offset & 0x0FF00) >> 4)) > 0x0FF) TOSU = TOSU 1; TOSH = ((TableStart & 0x0FF00) >> 4) ((offset & 0x0FF00) >> 4); if (((TableStart & 0x0FF) (offset & 0x0FF)) > 0x0FF) if ((TOSH 1) > 0x0FF) { TOSH = 0; TOSU = TOSU 1; } else TOSH = TOSH 1; Return
The block diagram for the PIC18 s program counter and stack is similar to that of the other PIC microcontrollers but incorporates the differences that have been discussed and is shown in Fig. 6.28. You can see that the 21-bit program counter can be updated from
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