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Microchip does not recommend the use of the option and tris instructions in the mid-range PIC microcontrollers. These instructions were originally created for the low-end PIC microcontrollers, which do not have the OPTION and TRIS registers mapped into speci c banks (as does the mid-range). Microchip, while continuing their use in the current mid-range PIC microcontrollers, may not continue them in future devices. As I have indicated elsewhere in the book, I personally don t recommend their use because they do not access all the PORT registers in all PIC microcontrollers. If you look at the bit pattern for the instruction:
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00 0000 0110 0fff
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Figure 7.16 The tris copy from w into the speci ed TRIS register.
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Figure 7.17 operation.
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The swapf nybble exchange instruction
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where fff is the PORT register written to by the instruction, you will see that the TRIS registers for PORTA (address 5), PORTB (address 6), and PORTC (address 7) are the only ones that can be written to. With PIC microcontrollers that have a PORTD (address 0x008) and PORTE (address 0x009), the tris instruction cannot be used because these TRIS registers cannot be accessed by the tris instruction. Despite this, there still are times when you may want to use the tris and option instructions, especially when debugging an application on a mid-range PIC microcontroller that was originally written to be programmed into a low-end PIC microcontroller. One of the most interesting instructions in the PIC microcontroller is the swapf instruction (see Fig. 7.17). This instruction exchanges (or swaps) the contents of the high and low nybbles of the source register and stores the value in w or back in the source register depending on the value of d in its invocation:
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swapf Register, d
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The most obvious use for swapf is to use it for displaying a byte as two ASCII nybbles. The code:
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swapf Register, w call movf call ; Move the Most Signi cant four bits into the ; Least Signi cant four bits of w NybbleDisplay ; Output the Least Signi cant four bits of ; w as an ASCII Character Register, w ; Move the byte into w without modi cation NybbleDisplay ; Display the Least Signi cant four bits of ; w as an ASCII Character
loads the least signi cant 4 bits of w with the digit to display before calling NybbleDisplay, which converts these 4 bits into an ASCII hex code representation.
THE MID-RANGE INSTRUCTION SET
The example code above will rst output the most signi cant 4 bits of the contents of Register followed by the least signi cant 4 bits. swapf does not modify any of the STATUS ags, which makes it useful in loading w without changing any of the STATUS ags. The code snippet:
swapf swapf Register, f Register, w
exchanges the high and low nybbles of Register and stores the result back into Register before exchanging them again and loading the contents into w. This double exchange returns the contents of Register to the original value for loading into WREG without modifying any of the STATUS register bits. The ability to load w with a register value without affecting the contents of the STATUS bits (speci cally the zero ag, which is modi ed by the movf instruction) is something that is taken advantage of in PIC microcontroller interrupt handlers. In the PIC18, data movement instructions have been included that do not modify any of the STATUS bits, so this application of swapf is not necessary in these PIC microcontroller processors. I recommend that you demonstrate the operation of the swapf instruction using the InsTemplate.asm program:
movlw movwf movlw movwf swapf swapf 0xF5 0x20 0x1F STATUS 0x20, f 0x20, w ; Load a register with a non-zero value
Set the Arithmetic STATUS bits
; Swap the value in 0x20 ; and load in w reg without affecting STATUS
After single-stepping through the program, you will see that the three arithmetic status bits (z, dc, and c) do not change although the value 0xF5 does change in address 0x20. The last two instructions used for data movement are the bcf and bsf instructions that reset or set a speci c bit in a register, respectively. The operation of the bcf instruction is shown in Fig. 7.18 and is speci ed in assembly language source code as:
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