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Table4: ; Set PCLATH Before Calculating Offset if ((TableEntries & 0x100) != 0) bsf PCLATH, 0 else
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THE MID-RANGE INSTRUCTION SET
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bcf PCLATH, 0 endif if ((TableEntries & 0x200) != 0) bsf PCLATH, 1 else bcf PCLATH, 1 endif if ((TableEntries & 0x400) != 0) bsf PCLATH, 2 else bcf PCLATH, 2 endif if ((TableEntries & 0x800) != 0) bsf PCLATH, 3 else bcf PCLATH, 3 endif if ((TableEntries & 0x1000) != 0) bsf PCLATH, 4 else bcf PCLATH, 4 endif addlw LOW TableEntries ; Calculate Offset btfsc STATUS, C ; If carry, goto the next Offset incf PCLATH, f movwf PCL TableEntries: dt Table , 0
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Throughout this chapter and the book, I have given you examples of typical processor code and how the PIC microcontroller s instruction set and features can be used to improve the operation of the code. In this case, I have given you a very general set of code, and I recommend that you always use it for your tables instead of the single instruction program counter update. Tables do not have to be only used for ASCII information, as I have shown in the examples above. They are the basis for computed address and are useful for conditional execution and execution state machines, as I will show later in the book.
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Interrupts Creating interrupt service routines (also known as interrupt handlers) for
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the mid-range PIC microcontroller differs from the approach taken for other processors, as a clear understanding of the application is required to ensure that when execution is returned to the previously running code the hardware is in exactly the same state it was left in. In traditional processors, the basic interrupt acknowledge operation and return from interrupt instructions save the context registers correctly, avoiding the need for the programmer to explicitly save them. The interrupt acknowledge and return from interrupt are very basic operations in the mid-range PIC microcontroller, which ts in with the RISC philosophy used to architect the device. Unfortunately, the process is complicated
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USING THE PIC MCU INSTRUCTION SET
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TABLE 7.3 CONTEXT REGISTERS AND THE BITS THAT COULD BE AFFECTED DURING AN INTERRUPT SERVICE ROUTINE REGISTER AFFECTED BITS
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WREG STATUS PCLATH FSR
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All IRP, RP1, RP0, Z, DC and C All Optional only if the interrupt service routine sets and uses FSR
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by the use of bank registers and execution pages as well as instructions that inconveniently change the context registers of the chip. There are some conventions that should be used to ensure that your interrupt handlers return execution with all context registers in the exactly same state as they were when the interrupt was acknowledged. The context registers in the mid-range PIC microcontroller are listed in Table 7.3 with bits that you should be concerned about. The list shouldn t be surprising, considering the discussion of bank addressing and interpage jumps that have been presented in this chapter. When starting an interrupt service routine, these four registers should be saved. Complicating the process is assuming that the register bank bits specify a bank other than the bank used to store the context register contents and if the PCLATH bits are not set to page 0 (where the interrupt service routine is located). The recommended entry code for the mid-range PIC microcontroller interrupt service routine (at address 4, as noted in the previous chapter) is:
org 4 Int: movwf _wreg ; Save the contents of WREG movf STATUS, w ; Save the contents of STATUS movwf _status movf PCLATH, w ; Save the contents of PCLATH movwf _pclath movf FSR, w ; Optional save the contents of FSR movwf _fsr movlw 0x1F ; Reset IRP, RP1 & RP0 (Assuming that the andwf STATUS, f ; registers accessed are in Bank 0) clrf PCLATH ; Reset PCLATH to execute out of rst page ; Test and Reset the f bit requesting the interrupt
Saving the contents of the FSR register is marked as optional because its contents only have to be saved if the interrupt service routine modi es the FSR in any way. The Test and Reset . . . code will be discussed elsewhere in the book, but I recommend that the interrupt source (if there are multiple possible sources) is checked and
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