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LIST R=DEC INCLUDE p18f2510.inc CBLOCK ENDC CONFIG CONFIG CONFIG CONFIG CONFIG CONFIG org ; 0x0
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OSC=INTIO67, FCMEN=OFF, IESO=OFF, PWRT=ON, BOREN=OFF, WDT=OFF WDTPS=1, MCLRE=OFF, LPT1OSC=OFF, PBADEN=OFF, CCP2MX=PORTC STVREN=OFF, LVP=OFF, XINST=OFF, DEBUG=OFF CP0=OFF, CP1=OFF, CP2=OFF, CP3=OFF, CPB=OFF WRT0=OFF, WRT1=OFF, WRT2=OFF, WRT3=OFF, WRTB=OFF, WRTC=OFF EBTR0=OFF, EBTR1=OFF, EBTR2=OFF, EBTR3=OFF, EBTRB=OFF 0
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Before starting to work on a new PIC microcontroller architecture, I have found the rst thing is to decide where variables are to be placed and how data is to be organized. In the mid-range PIC microcontroller devices, placing single and double byte variables in bank 0 cuts down on the number of execution bank changes that have to be made within the application. Array variable data is normally placed in bank 1 (or bank 2 or bank 3 is selected using the IRP bit), which can be addressed directly by the FSR register. Data for the low-end PIC microcontroller architecture is located similarly with bank 0 being used for single and double byte values and arrays placed in bank 1 or higher. In the PIC18 architecture, I follow a similar philosophy for single and double byte variable placement. These variables are always located in the rst 128 addresses of bank 0, allowing them to be addressed via the access RAM. PIC18 array variables are placed in the upper banks of memory where they can be accessed by the index (FSR) registers, which do not require special bank access. In each architecture I have chosen a method that allows me to access basic 1- and 2-byte variables directly without changing the bank register and accessing arrays using the basic capabilities of the FSR register. Data can be loaded and stored in the WREG register using the PIC18 movf, movlw, and movwf instructions. The important difference between these instructions and the other architecture s analogs is the addition of the access bit in the instruction bit patterns, which allows you to choose between using the bank register for accessing data or reading and writing the basic information directly. When a 1 is speci ed as the last parameter in the instruction, like:
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PC Program Counter Stack
Register Space
File Registers
Instruction Bit Pattern: 11101110 00ffkkkk 12345678 12345678 11110000 kkkkkkkk 12345678 12345678 Register Address Bus
STATUS WREG BSR
Instruction Operation: FSR# = Constant;
Fast Stack
Instruction Register/ Decode Second Instruction Register
Notes: This instruction is designed for FSR0, FSR1 and FSR2
Flags Affected None Instruction Cycles: 2
Figure 7.44 value.
The PIC18 lfsr instruction loads an FSR register with a constant
the BSR register is used to select the bank the variable i is located within. If a 0 or nothing is speci ed as the instruction s last parameter:
movf i, w
the value for i is taken out of the access bank or PIC18 addresses 0x000 to 0x7F for le registers or 0xF80 to 0xFFF for the special function registers (SFRs). If the access bit isn t present, then the access bank is selected by default (as if the access bit was zero). The new instructions added to the PIC18Cxx architecture are lfsr (Fig. 7.44), movlb (Fig. 7.45), and movff (Fig. 7.46). These instructions are used to specify
Register Space
PC Program Counter Stack ALU File Registers
Program Memory
Instruction Bit Pattern: 00000001 kkkkkkkk 12345678 12345678 Register Address Bus
STATUS WREG BSR
Instruction Operation: BSR = Constant;
Fast Stack FSR
Instruction Register/ Decode Second Instruction Register
Notes: Only least signficant four bits of the constant are stored in the BSR.
Flags Affected: None Instruction Cycles: 1
Figure 7.45 literal value.
The PIC18 movlb instruction loads the BSR register with a
PIC18 INSTRUCTION SET
Program Memory
PC Program Counter Stack ALU
Register Space
File Registers
Instruction Bit Pattern: 1 1 012345678f 12345678 0ffff ffffffs 1111ffff fffffffs Register Address Bus
STATUS WREG BSR
Instruction Operation: Destination Register = Source Register;
Fast Stack
Instruction Register/ Decode Second Instruction Register
Notes:This instruction allows data transfer anwhere in the PIC18Cxx Register Space.
Flags Affected: NoneInstruction Cycles: 2
Figure 7.46 The PIC18 movff instruction allows direct transfer of data between registers without temporarily saving the value in WREG.
addresses anywhere in the PIC18 s register space. The rst two instructions are used to load constant full register addresses into the FSR index register and the bank select register (BSR), respectively. lfsr loads a 12-bit constant into the speci ed FSR register as the start to a table. movlb loads a 4-bit constant into the BSR register that speci es which bank variables are to be taken from. The movff instruction is particularly useful because it does not change the STATUS register bits and does not affect the contents of WREG. I found that this instruction allows very simple string movement and data copies. For example, to copy 5 bytes of data from one string to another, the code is simply:
lfsr lfsr movlw Loop movff decfsz bra FSR0, SourceString FSR1, DestString 5 POSTINC0, POSTINC1 WREG, f, 0 Loop ; ; ; ; Point to the Start of the Strings Load WREG with 5 Copy String and Increment the FSR Registers
In the mid-range architecture, the same function would be accomplished by the following code:
clrf Loop movlw addwf movwf movf movwf movlw Count SourceString Count, w FSR INDF, w Temp DestString ; ; Reset the Offset Within the String Get the Current Source Element
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