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USING THE PIC MCU INSTRUCTION SET
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addwf movwf movf movwf incf movlw xorwf btfss goto
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Count, w FSR Temp, w INDF Count, f 5 Count, w STATUS, Z Loop
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In the mid-range PIC microcontroller string move code, note that the source and destination are located in the same bank pairs. If different bank pairs used for the two strings (such as bank 0 and bank 3), the code would become more cumbersome. This is not an issue with the PIC18 and its 12-bit FSR registers, which can be loaded explicitly. Most PIC18 code will not result in as dramatic improvements as this, but you can see where the movff instruction along with the ability to post-increment FSR registers can improve an application s code ef ciency (no matter how you measure it) signi cantly. I will discuss this feature in more detail later in this chapter. Along with accessing data in the register space, the PIC18 can also access its own program memory. The tblrd (Fig. 7.47) instruction will place the 16-bit contents of the program memory at the TBLPTR speci ed address into the TABLAT registers. TBLPTR is a 21-bit long address and instructions must have its least signi cant bit reset (clear) so the 16-bit address does not go over (straddle) a word boundary. Like the indexed addressing, the table reads and writes have options in which the table pointer is incremented or decremented as part of the equation.
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Instruction Bit Pattern: 00000000 000010xx See Notes: for xx coding Instruction Operation: if TBLRD * TABLAT = [TBLPTR] elseif TBLRD *+ TABLAT = [TBLPTR] TBLPTR = TBLPTR + 1 elseif TBLRD *- TABLAT = [TBLPTR] TBLPTR = TBLPTR - 1 elseif TBLRD +* TBLPTR = TBLPTR + 1 TABLAT = [TBLPTR] Flags Affected: None Instruction Cycles: 2
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Register Address Bus
TBLPTR BSR
Fast Stack FSR
Instruction Register/ Decode Second Instruction Register
Notes: TBLPTR is Optionally Updated During Instruction for Table/String Operations Table at Right Shows Operations and XX Coding.
Instruction xx tblrd * 00 tblrd *+ 01 tblrd *10 tblrd +* 11
Figure 7.47 memory data.
The tblrd instruction allows direct access to program
PIC18 INSTRUCTION SET
To carry out a program memory read, the following instruction sequence could be used:
movlw movwf movlw movwf movlw movwf tblrd movf : movf : UPPER ReadAddr TBLPTRU, 0 HIGH ReadAddr TBLPTRH, 0 LOW ReadAddr TBLPTRL, 0 * TABLATL, w, 0 ; ; ; Load the Top 5 Address Bits Load the Middle 8 Address Bits Load the Bottom 8 Address Bits
; ; ; ; ;
Read the Program Memory Process the Low Byte of the Program Memory Instruction Process the High Byte of the Program Memory Instruction
TABLATH, w, 0
In tblrd (and tblwt, which follows), a TBLPTR increment or decrement speci cation can be optionally put in. In Figure 7.47, I have included the four options and how the bit pattern is changed. Table write (tblwt, Fig. 7.48) instructions are available to write to the Flash program memory of PIC18 microcontroller architectures. Later in the book, I will show how this instruction is used to write to a PIC microcontroller s internal Flash registers or to external bus devices. The PIC18Cxx tblwt instruction must be terminated by a reset or interrupt.
Program Memory
PC Program Counter Stack ALU
Register Space
File Registers
Instruction Bit Pattern: 00000000 000011xx See Notes: for xx coding Instruction Operation: if TBLWT * [TBLPTR] = TABLAT elseif TBLWT *+ [TBLPTR] = TABLAT TBLPTR = TBLPTR + 1 elseif TBLWT *- [TBLPTR] = TABLAT TBLPTR = TBLPTR - 1 elseif TBLWT +* TBLPTR = TBLPTR + 1 [TBLPTR] = TABLAT
Register Address Bus
STATUS WREG
TBLPTR BSR
Fast Stack FSR
Instruction Register/ Decode Second Instruction Register
Notes: TBLPTR is Optionally Updated During Instruction for Table/String Operations Table at Right Shows Operations and XX Coding.
Instruction xx tblrd * 00 tblrd *+ 01 tblrd *10 tblrd +* 11
Flags Affected: None Instruction Cycles: Requires Interrupt or Reset to Complete
The tblwt instruction allows you to change program memory.
USING THE PIC MCU INSTRUCTION SET
Indexed addressing The low-end PIC microcontroller architecture s FSR register
or pointer can access every address in the register space, but there is a maximum of 128 addresses built into the architecture, broken into blocks of 16 bytes apiece. The midrange chips have an address space of up to 512 addresses but require an extra addressing bit to access the up to 96 bytes in each block. These restrictions make it dif cult to create an application that can access a large amount of data easily in a single, continuous block of memory. The PIC18 architecture does not have these restrictions with its single, large address space and SFRs at the high end range, resulting in a large number of le registers that can be accessed directly by the multiple index pointers. Not only can each index pointer access any address in the 4,096 register address space, but there are increment and decrement options as well as an offset option that will allow you to work with stacks or arrays much more ef ciently than if you were working in one of the other architectures. The PIC18 provides much more advanced capabilities than the low-end PIC microcontroller architecture while still retaining its philosophy: being able to access every address in the register space. Each of the three index pointers available in the PIC18 microcontroller architecture consists of two registers. The low register (marked with an L at the end of its name) provides access to the lower 8 bits of the address while the high register (marked with an H) provides access to the upper 4 bits. Together, the registers point to an address in the register space and can be initialized either by traditional movlw, movf, or movwf instructions or the lfsr instruction can be used to set the 12 address bits in a single instruction. Despite being larger than the mid-range index register and IRP bit, you will probably nd that the PIC18 FSR registers can be initialized in fewer instructions. As with the low-end and mid-range architectures, if you are going to access the byte addressed by the index pointer, you could read from or write to the INDF register, which would return the contents of the register pointed to by the FSR, but you also have four additional INDF registers that you can take advantage of to simplify the task of using the index pointer. The four additional PIC18 INDF registers for each index pointer include POSTINC, which increments the pointer after the access, POSTDEC, which increments the pointer after the access, PREINC, which increments the pointer before the access takes place, and PLUSW, which adds the contents of WREG to the index pointer for the address. Each of these indexed addressing registers provides you with additional capabilities that will come in very handy when you are implementing different functions using the index pointers. To show what I mean, consider the case of a simple, single byte array. If you were going to use the index register to point to an array, you will probably nd that once you point to the start of the array you will never have to modify the contents of the index register because of the ability to access a byte offset speci ed within the WREG using the PLUSW register. For example, consider the case of the array variable ArrayVar, which has ten elements, and the FSR register, which was pointing to the rst element in the array. If you wanted to load the variable i with the contents of third element in the array variable in the mid-range PIC microcontroller, you would use the code:
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