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Instruction Register/ Decode Second Instruction Register
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Notes: Rcall 2 s Complement Offset is Added to the Address of the Next Instruction. Note, the 2 s Complement Offset MUST be even
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Flags Affected: None Instruction Cycles: 2
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Figure 7.53 The rcall instruction allows accessing subroutines that start 64 to +63 instructions from the current program counter location.
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If you were to enter the code into the PIC18InsTemplt.asm project and build it, you would get a warning indicating that the instruction cannot start at an odd address. To x the problem, you have to multiply the offset by 2, producing the code:
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movlw 47 decfsz WREG, f, 0 bra $ - (1 * 2) ; Loop 47x3 instruction cycles
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which will build cleanly and you can simulate to see that it actually takes 141 (47 times 3) instructions. If you want to avoid this difference between the PIC18 and the other devices, I would recommend that you always use labels and never use relative addressing. Above, I indicated that there was a one word goto instruction called bra (branch always). This instruction type (shown in Fig. 7.54) changes the program counter according to the 2 s complement offset provided in the instruction according to the formula:
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PCnew = PCcurrent + 2 + Offset
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where PCcurrent is the current address of the executing branch instruction. The 2 added to PCcurrent results in the address after the current one. Offset is the 2 s complement value, which is added or subtracted (if the Offset is negative) from the sum of PCcurrent and 2. The MPASM assembler computes the correct offset for you when the destination of a branch instruction is a label. MPASM computes the 2 s complement offset using the formula:
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Offset = Destination (Current Address)
PIC18 INSTRUCTION SET
Program Memory
PC Program Counter Stack ALU
Register Space
File Registers
STATUS WREG BSR
Fast Stack FSR
Instruction Bit Pattern: BC 12345678 12345678 11000010 nnnnnnnn BNC 12345678 12345678 11100011 nnnnnnnn BN 12345678 12345678 11100110 nnnnnnnn BNN 12345678 12345678 11100011 nnnnnnnn BOV 12345678 12345678 11100100 nnnnnnnn BNOV12345678 12345678 11100101 nnnnnnnn BZ 12345678 12345678 11100000 nnnnnnnn BNZ 12345678 12345678 11100001 nnnnnnnn BRA 12345678 12345678 11010nnn nnnnnnnn Instruction Operation: BC/BNC: Branch on Carry Flag BN/BNN: Branch on N Flag BOV/BNOV: Branch on OV Flag BZ/BNZ: Branch on Zero Flag BRA: Branch Allways
Instruction Register/ Decode Second Instruction Register
Notes: Offset n is a Two s Complement Number
Flags Affected: None Instruction Cycles: 2 if Branch Taken 1 otherwise
Figure 7.54 The branch instruction can access addresses 512 to +511 instructions from the current program counter location.
If the destination is outside the range of the instruction it is agged as an error by the MPASM assembler. Along with the nonconditional branch, there are 8 conditional branch instructions available in the PIC18 and they are shown in Fig. 7.54. They are branch on zero ag set (bz), branch on zero ag reset (bnz), branch on carry ag set (bc), branch on carry ag reset (bnc), branch on negative ag set (bn), branch on negative ag reset (bnn), branch on over ow ag set (bov), and branch on over ow ag reset (bnov). These instructions are equivalent to the branch on condition instructions found in other processors. These instructions behave similarly to the bra instruction except that they have 8 bits for the offset address (to the bra instruction s 11). This gives the instructions the ability to change the program counter by 64 to +63 instructions. The last new feature of the PIC18 architecture that is different from the other architectures is the fast stack, in which WREG, STATUS, and BSR registers are saved nonconditionally upon the interrupt acknowledge and vector jump and conditionally during a subroutine call instruction. These registers can be optionally restored after a return or ret e instruction.
Tables PIC18 tables are executed as: TableRead: movwf TableOff, 0 bcf STATUS, C, 0 rlcf TableOff, w, 0
First Calculate if past rst 256 addresses and by how much
USING THE PIC MCU INSTRUCTION SET
addlw Table & 0xFF movf STATUS, w, 0 andlw 1 btfsc TableOff, 7, 0 addlw 1 addlw (Table >> 8) & 0xFF movwf PCLATH, 0 movf STATUS, w, 0 andlw 1 addlw UPPER Table movwf PCLATU, 0 rlcf TableOff, w, 0 addlw LOW Table movwf PCL, 0 Table: dt ...
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