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The reason for producing OTP devices is probably not obvious when you consider that the advantage of the EPROM is its ability to be erased and reprogrammed using ultraviolet light, which cannot pass through opaque plastic. It seems to make more sense to go with a mask ROM or fusible link PROM device. OTP devices actually ll a large market niche, as windowed ceramic packages cost roughly ten times what a plastic package costs, the EPROM memory is more reliable than PROM, and in most microcontroller applications and products, the device will never be reprogrammed. So, by using OTP packaging, the part can be programmed at the product assembly site, will be electrically identical to the part used to develop the application, and is very cost effective for quantities less than the break-even point for mask ROM. When you look at some manufacturers and distributors catalogs, you will discover that the term OTP is used in situations that don t match what is described here (that is, for chips that do not have EPROM memory). In the past few years, OTP has come to mean any programmable part that is not in a windowed package. Remember that if you are ever confused as to the appearance of a packaged part, you can look it up in the manufacturer s datasheets. An improvement over UV erasable EPROM technology is electrically erasable PROM (EEPROM). This type of nonvolatile memory is built with the same technology as EPROM, but the oating gate s charge can be removed by circuits on the chip and no UV light is required. There are two types of EEPROM in use in microcontrollers. The rst type is simply known as EEPROM and allows each bit (and sometimes byte) of the program memory array to be reprogrammed without affecting any other cells in the array. This type of memory rst became available in the early 1980s and found its way into microcontrollers in the early 1990s. EEPROM has been very successful when implemented in small, easy-to-access packages. In the late 1980s, Intel introduced a modi cation to EEPROM that was called Flash. The difference between Flash and EEPROM is Flash s use of a bussed circuit for erasing the cells oating gates rather than making each cell independent. This reduced the cost of the EEPROM memory and speeded up the time required to program a device (rather than having to erase each cell in the EEPROM individually, the Flash erase cycle erases all the memory in the array, which takes as long as for 1 byte). If you ve spent some time programming PC applications, you ve probably never worried about the space variables and data structures take up. Most modern PC languages will allow effectively unlimited direct storage. If you looked at a PIC microcontroller datasheet before reading this book, you would probably have been shocked to see tens to a few hundreds of bytes of variable memory in the le registers area of the chip, and you probably wondered how complex applications could be written for the device. Creating complex applications with limited variable RAM in microcontrollers is not dif cult, although large arrays cannot be implemented without external memory. Throughout this book, I will present some very substantial applications without requiring any external memory. These applications also include sophisticated text-based user interfaces that take advantage of the PIC microcontroller s ability to read program memory for text output data. Variable storage in the microcontrollers is implemented as static random-access memory (SRAM), which will retain the current contents only as long as power is supplied
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Figure 1.17 circuitry.
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to it and hence is referred to as volatile memory. Each bit in an SRAM memory array is made up of the six transistor memory cells shown in Fig. 1.17. This memory cell circuitry (probably known to you as a ip- op ) will stay in one state until the write enable transistor is enabled and the write data is used to set the state of the SRAM cell. The P-channel/N-channel transistor pair on the write side of the ip- op will hold this value as a voltage level because it will cause the P-channel/N-channel transistor pair on the read side to output the complemented value. This complemented value will then be fed back to the write side s transistors, which complements the value again, resulting in the actual value that had been set in the ip- op. This circuit is really a pair of inverters feeding back to each other, as I ve shown in Fig. 1.18. Reading data is accomplished by asserting the read enable line and inverting the value output (because the read side contains the inverted write side s data). The driver to the SRAM cell must be able to overpower the output of the inverter in order for it to change the cell s state. Once a value has been set in the inverters feedback loop, it will stay there until changed. This method of implementing a SRAM cell is well suited to a microcontroller
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