barcode reader project in asp.net THE TMR0/WATCHDOG TIMER PRESCALER in Software

Drawing QR Code in Software THE TMR0/WATCHDOG TIMER PRESCALER

THE TMR0/WATCHDOG TIMER PRESCALER
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The prescaler is a power of 2 counter that can be selected for use with either the watchdog timer or TMR0. Its purpose is to divide the incoming clock signals by a softwareselectable power of 2 to allow the 8-bit TMR0 to time longer events or increase the watchdog delay from 18 ms to 2.3 s. The prescaler s operation is controlled by 4 bits contained within the OPTION register. PSA selects whether the watchdog timer uses the prescaler (when PSA is set), or TMR uses the prescaler (when PSA is reset). Note that the prescaler has to be assigned to either the watchdog timer or TMR0; fortunately, both functions are able to execute with no prescaler or with the prescaler s delay count set to 1, which results in no delay. The prescaler itself is a power or 2 counter, with the trigger point selected by the PSO, PS1, and PS2 bits of the OPTION register. I call prescaler operation a power of 2 because the number of cycles delay is a function of the PSA bit value. Table 9.10 shows
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TABLE 9.10 PS2:0 PRESCALER VALUES TO DELAYS TMR0 DELAY
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PRESCALER (WDT) DELAY
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000 001 010 011 100 101 110 111
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1 cycle (1:1) 2 cycles (1:2) 4 cycles (1:4) 8 cycles (1:8) 16 cycles (1:16) 32 cycles (1:32) 64 cycles (1:64) 128 cycles (1:128)
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2 cycles (1:2) 4 cycles (1:4) 8 cycles (1:8) 16 cycles (1:16) 32 cycles (1:32) 64 cycles (1:64) 128 cycles (1:128) 256 cycles (1:256)
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INTERRUPT OPERATION
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Mux TMR0 Mux
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Watch Dog PSA
PSA Reset
Oscillator Clock T0CKI Pin TOSE
T0CS 0 Mux
Prescaler (PS2:PS0)
/2 Synch
Figure 9.26 The TMR0/WDT prescaler can be devoted to either device.
the prescaler cycle delay for varying values of the PS# bits. In this table I noted that the prescaler delay is double when it is applied to TMR0. For PS2 PS0 equal to 011, one of every eight clock cycles input into the prescaler will be passed to the device the prescaler is driving. The watchdog timer and TMR0 block diagrams can be combined with the prescaler to show how the functions work. This is shown in Fig. 9.26 and shows the synchronizer (which divides the TMR0 input by 2) in place as part of the path to the prescaler.
Interrupt Operation
In mid-range PIC microcontrollers, the INTCON register is the focal point for interrupts. This register (de ned in Table 9.11) is used to globally enable interrupts, as well as to control the response to different interrupt inputs. The register consists of four different bit types and is located at address 0x0B in all active register banks. The bit usage is similar for all mid-range devices. The GIE bit must be set for interrupt requests to be passed to the processor. This bit can globally mask or allow (unmask) interrupt requests going to the processor. If a critical section of code is being entered, by resetting this bit, the interrupt request will be ignored until GIE is set, allowing the code to execute without being interrupted. The INTCON bit names the grounds in E that are the interrupt enable ags. When these bits are set, any incoming interrupt requests will set the corresponding interrupt request active ags, which have a bit name that ends in F. The request active ag must be reset in hardware and is not reset automatically by the operation of the interrupt acceptance (which I also call acknowledgment elsewhere in this book). In addition, the requesting hardware may have to be reset before the F (request active ag) can be reset. Using the block diagram in Fig. 9.24 as a model, if the E bit for a particular interrupt source is set, then interrupt requests, which have set their appropriate F bits, will request an interrupt of the PIC microcontroller processor if the GIE bit is set.
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