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TABLE 9.11 MID-RANGE PIC MICROCONTROLLER INTCON REGISTER DEFINITION BIT DESCRIPTION
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GIE global interrupt enable Device-speci c T0IE TMR0 over ow interrupt enable INTE RBO/INT pin interrupt enable RBIE PORTB input change interrupt enable TOIF TMR0 over ow interrupt request active INTF RBO/INT pin interrupt request active RBIF PORTB input change interrupt request active
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When the processor receives the interrupt request, it completes the current instruction before jumping to the interrupt vector. Instruction execution in the PIC microcontroller can be one or two cycles long, and when added to the two-instruction delay for calling the interrupt handler, the total delay (which is known as interrupt latency) is three or four instruction cycles. In mid-range devices, the interrupt vector s address is 0x0004 for all interrupt sources. What happens during execution is shown in Fig. 9.27. As was noted earlier, when the processor jumps to the interrupt vector, the GIE bit is reset. The return address (the address of the instruction after the interrupted one) is saved on the program counter stack. With GIE reset, no subsequent interrupts can interrupt the interrupt handler s execution. Because of the lack of a data stack in the PIC microcontroller s processor, I do not recommend that the GIE bit be set within the interrupt handler. Instead, it should be set by the ret e instruction after completing servicing of the current interrupt. If the timing delay of restoring the context registers, executing ret e, jumping back to the interrupt
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Figure 9.27 The PIC microcontroller responds to an active interrupt signal by rst storing the address of the next instruction to execute on the program counter stack.
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handler, and then storing the context registers again is too long, then I recommend that you poll the interrupt request ags before executing the ret e and jump to the appropriate service routine rather than returning to the mainline execution. I should point out that this section is hardware-centric. Back in Chap. 7 I discussed the assembly-language code required for saving and restoring the context registers for the various PIC microcontroller families. Interrupts will execute and return properly from any instruction or instruction combination. At one time there were reports that mid-range interrupts would have problems if they were acknowledged after a PCL update, but this is not true; there are no PIC microcontroller hardware de ciencies on which interrupts can execute. The only issue will be the application software. In mid-range parts, there are three interrupt sources that are handled from within the INTCON register. The TOIF and TOIE bits allow an interrupt request when TMR0 over ows (equals 255 or 0x0100). The second responds to an input on the RBO (usually marked RBO/INT by Microchip), when the input on the pin goes high or low (depending on the STATUS register state). The last interrupt source, PORTB change interrupt, requires some comments because there is some confusion about the operation of this interrupt. The port B change interrupt will request an interrupt if any of the RB7 RB4 pins (which are in input mode) change state. The pins will not request an interrupt if they are in output mode. To reset the interrupt, port B must be read to set the input state before resetting the RBIF ag. If this is not done, the RBIF ag will remain set and request an interrupt, no matter how you try to reset it. Along with these three interrupt sources, in many PIC microcontrollers there are a number of built-in peripherals that can request interrupts to allow these additional sources. Bit 6 can be used as another E bit (with the F bit in another register) or an enable bit for the PIE and PIR registers. There may be one or two sets of PIE and PIR registers, according to the features built into the PIC microcontroller. Unfortunately, there doesn t seem to be any convention for how the bits are set. But by looking at the PIC microcontroller device datasheet, you will get a bit speci cation with the interrupt bits.
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