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TABLE 13.1 REGISTER
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PIC18 RTOS TASK CONTEXT REGISTERS COMMENTS
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WREG STATUS BSR PCLATH PCLATU TBLPTRH TABLAT PRODL PRODH FSR0L/FSR0H FSR1L/FSR1H TOSL/TOSH/TOSU Top three program counter pushes on the stack
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the access bank registers. This allows me to set or restore the special-function registers without having to cross bank boundaries (which simpli ed development of the RTOS considerably). This is probably the largest area of inef ciency in the RTOS. If the TIB s special-function register area would pass data to and from the saved TIB rather than the access bank copy, quite a few instructions and cycles could be saved in the RTOS s execution and task switches. The ability to access the program counter s stack in the PIC18 is what sets this architecture apart from the others and makes the RTOS possible. For this application, I only save the top three elements of the stack and not the total 31. The primary reason for doing this is to save le registers. If all eight possible tasks saved all 31 program counter stack elements, then 744 bytes would be required. By cutting the saved value down to only the top three, I only require 72 le registers to save the task s stack. Saving the top three program counter stack elements means that the task can be nested down two levels of subroutines when the RTOS is active. This means that the task s mainline can call a subroutine and that subroutine can call another subroutine. Recursive subroutines cannot be implemented at all in the RTOS. There is one case to watch out for, and that is when a new task is started. When the TaskStart macro is invoked, it pushes the starting address onto the stack. I did this because it allowed me to simply copy data from one TIB into a new one that I had set up for it. It also meant that I would not have to make space in any other registers when the RTOS is invoked.
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TABLE 13.2 BITS
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Task operating mode: 11 able to execute 10 task is waiting for a message to be sent 01 task has sent a message and is waiting for it to be acknowledged 00 task is waiting for an interrupt request
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Task priority 11 highest : 00 lowest
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Task operating indicator, speci c to the task operating mode bits 7 6 1x 01 00 Task operating indicator bits function Bits are all zeros Bits contain the task the message has been sent to Bit ##
The rst byte of the TIB is the task byte. This byte is used to indicate to the RTOS the status of a speci c task. The task byte is de ned in Table 13.2, and the interrupts supported for the task to wait for are listed in Table 13.3. All the possible PIC18 interrupt request sources are accounted for except for the INT1 request. This request was left off because it is put in a register that doesn t follow the conventions of the other bits, and I wanted to have a special purpose value that is used to ag the RTOS that an operating system request is required. The interrupts are run in normal, not priority, mode. Priority mode never must be enabled with the RTOS because the code is designed for a single entry point for interrupts and code. Enabling interrupts will cause a second entry point that will result in task data being saved incorrectly when the interrupt request is acknowledged. When using interrupts with this RTOS, make sure that you only access the E bits to set them to enable the interrupt request. When an interrupt request is acknowledged by the RTOS, the E ag is also reset by the RTOS, except in the case of TMR0. For all interrupts except for TMR0, the tasks will have to enable the interrupts and reset the hardware after the request has been acknowledged. This means setting up the hardware and setting the E ag to enable the interrupt. TMR0 is enabled within the RTOS and will interrupt the application once every 16.384 ms (when running with a 4-MHz clock). This interrupt can be waited on, but
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