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DEVELOPING A QUALIFICATION PLAN
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Part of the requirements that you de ne for your application should be an application quali cation plan. This plan consists of a list of tests that the application must pass before you can consider it ready for use. In the list of quali cation tests that I present in this section, some items may seem obvious, but part of the purpose of the quali cation plan is to give you a checklist for when you build other units or instruct others on how to build the application. A typical quali cation plan would consist of
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1 Test for the power supply to supply 4.75 to 5.25 V of regulated power at the required 2 3 4 5 6
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current load. _MCLR pulled to a high logic level. The built-in oscillator runs when both OSC1 and OSC2 are probed. User interface output functions are at the correct initial state on power-up. User interface output functions respond correctly to user inputs. Application outputs respond to user inputs as expected.
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7 Application outputs respond to timer or application input events as expected. 8 Application test can detect all functional failures. 9 Reliability calculations have been performed to ensure that the application will not 10 11 12 13
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fail before its expected life is nished. Environmental quali cation. FCC, ESD, CISPR, CE, BABT, and other emissions and regulatory testing. User documentation is complete and correct. Manufacturer documentation is complete and correct.
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The rst three points of this list (checking power, reset, and clocking) may seem to be obvious and unnecessary, but I would argue that they are needed to ensure that the application will work reliably. If the application isn t executing, then they should be the rst things that are looked at. The power range that I speci ed in the preceding list probably seems quite restricted, especially with the wide input voltage ranges available to the PIC microcontroller; but you should understand what the operating conditions are of other chips of the circuit and nd out what their tolerances of input voltages are. Many active integrated circuits only work reliably within the 5 percent window that I have speci ed in the requirements list. For many different kinds of inputs, a simple digital multimeter or logic probe will not be suf cient. Ideally, an oscilloscope or logic analyzer should be used to look at the actual I/O and con rm that it is correct. If you do not have access to these tools, then you should rigorously simulate the application to make sure that all timings are correct. In most cases I would not consider it to be acceptable to qualify an application by seeing that it works when it is connected to another piece of hardware. You may get variances in the hardware that you are using that work in one application and do not work in another. For example, you may have a problem with a bit banging RS-232 interface depending on the tolerance of the clock that is used. If a three times sample algorithm, as I have discussed elsewhere in this book, is used, then the maximum a bit can be out is 30 percent at the end of the second to last bit. In 8-N-1 transmission, this is bit 7 of the application. In this case, the error after 9 bits can only be 30 percent or an error of 3.33 percent in the application clocking. Depending on the oscillator, 3.33 percent accuracy is pretty easy to get but what if the device you are communicating with uses the same bit banging serial algorithm Depending on the hardware and the situation, one device can be out by as much as 6.67 percent, and the two devices will communicate with each other. To avoid this type of problem, I would specify clocking accuracy that does not exceed one-third of the worst-case error. In the preceding example, this is 1.11 percent again not very hard to get with most clocking schemes available for the PIC microcontroller, but something to be aware of. This discussion on clocking brings up the point of guardbanding and what is the appropriate amount of spacing, slack, or slop you can have in your application s timing and still have it work reliably. In the preceding example, going with the rule of thumb, a 1.11 percent timing margin or a 100 percent error timing margin is allowed for a device s speci ed clock to be in error.
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