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WRERR WREN WR RD
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Note: These bits will be in different locations in the EECON1 register of different devices.
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Using these EEPROM registers, a read can be implemented using the code
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movf / movlw bcf movwf bsf bsf bcf movf address/ADDR, w STATUS, RPO EEADR STATUS, RPO EECON1, ^ 0x08, RD STATUS, RPO EEDATA, w
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w = EEPROM [address/ADDR]
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In this example code, it is assumed that these registers are in banks 0 and 1, which is true for the 16F84. For devices such as the 16F87x, however, where the ADC registers use these addresses, the EEPROM register addresses are actually in banks 2 and 3. The read operation above has to have a bsf STATUS, RP1 at the start and bcf STATUS, RP0 at the end, as shown below:
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movf /movlw bsf bcf movwf bsf bsf bcf movf bcf address/ADDR, w STATUS, RP1 ; STATUS, RP0 EEADR ^ 0x0100 STATUS, RPO EECON 1 ^ 0x0180, RD STATUS, RPO EEDATA ^ 0x0100, w ; STATUS, RP1
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Registers in Bank 3
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w = EEPROM [address/ADDR]
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Write operations are similar but have two important differences. The rst is that the operation can take up to 10 ms to complete, which means that the WR bit of EECON1 has to be polled for completion or in the EPROM interrupt request hardware enabled. The second difference is that a timed write has to be implemented to carry out the operation. Code to do an EPROM write could be
movlw /movf bcf movwf movlw /movf movwf bsf bsf bcf movlw movwf movlw movwf bsf bsf constant/DATA, w STATUS, RPO EEDATA address/ADDR, w EEADR STATUS,RPO EECON1 ^ 0x080, WREN INTCON,GIE 0x055 ; EECON2 ^ 0x080 ; 0x0AA ; EECON2 ^ 0x080 ; EECON1 ^ 0x080, WR ; INTCON, GIE
CRITICAL SECTION
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btfsc goto bcf bcf bsf
EECON1 ^ 0x080, WR ; $ - 1 ; EECON1 ^ 0x080, WREN STATUS, RPO INTCON, GIE
Poll for Operation Ended
For the devices with the EE access registers in banks 2 and 3, this code is modi ed in the same manner as the EEPROM read code was above. Note that EEPROM cannot be accessed in any way until WR is reset; otherwise, there will be a WRERR. The critically timed code (highlighted as CRITICAL SECTION in the example code) is used to indicate to the EEPROM access control hardware that the application is under control and that a write is desired. Any deviation in these instructions (including interrupts during the sequence) will cause the write request to be ignored by the EEPROM access control hardware. Instead of polling, after the WR bit is set, the EEIE interrupt request bit can be set. Once the EEPROM write has completed, then the EEIF le is set, and the hardware interrupt is requested. For MPLAB ICD enabled Flash devices, the program memory can be read or written to in a similar way to EEPROM data memory. The difference is the inclusion of the EEPGD bit in EECON1 that is not present in the devices with just EEPROM data memory. In the devices that do have programmable data and program memory, this bit always should be set (program memory) or reset (data memory) according to the memory access. Along with inclusion of the EEPGD bit, there are also two additional registers used to address and access the greater than 8-bit data and number of address bits. These bits are known as (not too surprisingly) EEADRH and EEDATAH. Note that the maximum data value for EEDATAH is 3F because 14 bits per instruction is used for program memory. To read to program memory, the following code is used for the 16F87x. Note the two nops to allow the operation to complete before the instruction is available for reading.
bsf movlw /movwf movwf movlw /movwf movwf bsf bsf bsf nop nop bcf movf movwf movwf movwf bcf STATUS, RP1 LOW address/ADDR, w EEADR ^ 0x0100 HIGH address/ADDR, w EEADRH ^ 0x0100 STATUS, RPO EECON1 ^ 0x0180, EEPGD EECON1 ^ 0x0180, RD ; ; STATUS, RPO EEDATA, w ----; EEDATAH, w ----; STATUS, RP1
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