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Along with TMR0, many PIC microcontrollers have an additional 16-bit (TMR1) and 8-bit (TMR2) timer built into them. These timers are designed to work with the compare/ capture program hardware feature. Along with enhancing this module, they also can be used as straight timers within the application. TMR1 (Fig. 16.3 shows the block diagram
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0 T1CKPS1: T1CKPS0
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_T1SYNCH
FOsc/4
TMR1IF
TMR1L
TMR1H
TMR1IE
TMR1 Interrupt Request
TMR1ON
TMR1 block diagram.
of the timer) is a 16-bit timer that has four possible inputs. What is most interesting about TMR1 is that it can use its own crystal to clock the timer. This allows TMR1 to run while the PIC microcontroller s processor is asleep. To access TMR1 data, the TMR1L and TMR1H registers are read and written. Just as in TMR0, if the TMR1 value registers are written, the TMR1 prescaler is reset. A TMR1 interrupt request (TMR1IF) is made when TMR1 over ows. TMR1 interrupt requests are passed to the PIC microcontroller s processor when the TMR1IE bit is set. TMR1IF and TMR1IE normally are located in the PIR and PIE registers. To request an interrupt, along with TMR1IE and GIE being set, the INTCON PIE bit also must be set. To control the operation of TMR1, the T1CON register is accessed with its bits de ned as shown in Table 16.2. The external oscillator is designed for fairly low-speed real-time clock applications. Normally, a 32.768-kHz watch crystal is used, along with two 33-pF capacitors. Additionally,
TABLE 16.2 BIT
T1CON REGISTER BIT DEFINITION DESCRIPTION
7 6 5 4
Unused T1CPS1 T1CPS0 Select TMR1 prescaler value 11 1:8 prescaler 10 1:4 prescaler 01 1:2 prescaler 00 1:1 prescaler
3 2 1 0
T10SLEN Set to enable TMR1 s built-in oscillator. T1SYNCH When TMR1CS is reset, the MR1 clock is synchronized to the instruction clock. TMR1CS When set, external clock is used. TMR1ON When set, TMR1 is enabled.
PIC MCU OPTIONAL HARDWARE FEATURES
T1OSCO
Crystal
T1OSCI
Cext
Figure 16.4 TMR1 can be driven by its own separate 32.768-kHz oscillator.
100- or 200-kHz crystals could be used with TMR1, but the capacitance required for the circuit changes to 15 pF. The TMR1 oscillator circuit is shown in Fig. 16.4. When TMR1 is running at the same time as the processor, the T1SYNCH bit should be reset. This bit will cause TMR1 to be synchronized with the instruction clock. If the TMR1 registers are to be accessed during processor execution, resetting T1SYNCH will make sure that there are no clock transitions during TMR1 access. T1SYNCH must be set (no synchronized input) when the PIC microcontroller is in sleep mode. In sleep mode, the main oscillator is stopped, stopping the synchronization clock to TMR1. In the PIC18 devices, TMR1 can be speci ed as the processor clock. This feature is one way to implement a low-current operating mode (the PIC microcontroller will run while drawing less than 1 mA of current) without disabling the entire device and its builtin functions. Note that returning to the normal program oscillator will require the 1024-instruction-cycle and optional 72-ms power-up reset delay that occurs when the PIC microcontroller clock starts up. The TMR1 prescaler allows 24-bit instruction cycle delay values to be used with TMR1. These delays can be either a constant value or an over ow, similar to TMR0. To calculate a delay, the formula
Delay = (65,536 TMR1Init) x prescaler / T1frequency
is used, where the T1frequency can be the instruction clock, TMR1 oscillator, or an external clock driving TMR1. Rearranging the formula, the TMR1init initial value can be calculated as
TMR1Init = 65,536 (Delay x T1Frequency / prescaler)
When calculating delays, the prescaler will have to be increased until the calculated TMR1Init is positive this is similar as to how the TMR0 prescaler and initial value are calculated for TMR0.
TMR2
TMR2 is used as a recurring event timer (see Fig. 16.5). When it is used with the CCP module, it is used to provide a PWM timebase frequency. In normal operations, it can be used to create a 16-bit instruction cycle delay.
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