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TMR1IF
TMR2 block diagram.
TMR2 is continually compared against the value in PR2. When the contents of TMR2 and PR2 match, TMR2 is reset, and the event is passed to the CCP as TMR2 Reset. If the TMR2 is to be used to produce a delay within the application, a postscaler is incremented when TMR2 overflows and eventually passes an interrupt request to the processor. TMR2 is controlled by the T2CON register, which is de ned in Table 16.3. The TMR2 register can be read or written at any time with the usual note that writes cause the prescaler and postscaler to be zeroed. Updates to T2CON do not affect the TMR2 prescaler or postscaler. The timer itself is not synchronized with the instruction clock like TMR0 and TMR1 because it can be used only with the instruction clock. This means that TMR2 can be incremented on a 1:1 instruction clock ratio. PR2 contains the reset, or count up to value. The delay before reset is de ned as
Delay = prescaler x (PR2 + 1) / (Fosc / 4)
TABLE 16.3 BIT
T2CON REGISTER BIT DEFINITION DESCRIPTION
7 6 5
Unused TOUTPS3 TOUTPS0 TMR2 postscaler select 1111 16:1 postscaler 1110 15:1 postscaler . . . 0000 1:1 postcaler
2 1 0
TMR2ON When set, TMR2 is enabled T2CKPS TMR2 prescaler selection bits 1x 16:1 prescaler 01 4:1 prescaler 00 1:1 prescaler
PIC MCU OPTIONAL HARDWARE FEATURES
If PR2 is equal to zero, the delay is
Delay = (prescaler x 256) / (Fosc / 4)
I do not usually calculate TMR2 delays with an initial TMR2INIT value. Instead, I take advantage of the PR2 register to provide a repeating delay and just reset TMR2 before starting the delay. To calculate the delay between TMR2 over ows (and interrupt requests), the following formula is used:
Delay = (prescaler x [PR2 + 1|256]) /((Fosc / 4) x postscaler)
Interrupts use the TMR2IE and TMR2IF bits that are similar to the corresponding bits in TMR1. These bits are located in the PIR and PIE registers. Because of the exact interrupt frequency, TMR2 is well suited for applications that provide bit banging functions such as asynchronous serial communications and PWM signal outputs.
Compare/Capture/ PWM (CCP) Module
Included with TMR1 and TMR2 is a control register and a set of logic functions (known as the CCP) that enhances the operation of the timers and can simplify your applications. This hardware may be provided singly or in pairs, which allows multiple functions to execute at the same time. If two CCP modules are built into the PIC microcontroller, then one is known as CCP1 and the other as CCP2. In the case where two CCP modules are built in, then all the registers are identi ed with the CCP1 or CCP2 pre x. The CCP hardware is controlled by the CCP1CON (or CCP2CON) register, which is de ned in Table 16.4. The most basic CCP mode is capture, which loads the CCPR registers (CCPR14, CCPR1C, CCPR2H, and CCPR2L) according to the mode the CCP register is set in. This function is illustrated in Fig. 16.6 and shows that the current TMR1 value is saved when the speci ed compare condition is met. Before enabling the capture mode, TMR1 must be enabled (usually running with the PIC microcontroller clock). The edge detect circuit in the gure is a 4:1 multiplexor, which chooses between the prescaled rising-edge input or a falling-edge input and passes the selected edge to latch the current TMR1 value and optionally request an interrupt. In capture mode, TMR1 is running continuously and is loaded when the condition on the CCPx pin matches the condition speci ed by the CCPxMS:CCPxM0 bits. When a capture occurs, then an interrupt request is made. This interrupt request should be acknowledged and the contents of CCPRxH and CCPRxL saved to avoid having them written over and the value in them lost.
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