barcode reader application in asp.net COMPARE/CAPTURE/PWM (CCP) MODULE in Software

Making QR-Code in Software COMPARE/CAPTURE/PWM (CCP) MODULE

COMPARE/CAPTURE/PWM (CCP) MODULE
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TABLE 16.4 BIT
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CCPXCON REGISTER BIT DEFINITIONS FUNCTION
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Unused DC1B1 DC1B0 CEPST signi cant 2 bits of the PWM compare value. CCP1M3 CCP1M0 CCP module operating mode 11xx PWM mode 1011 Compare mode, trigger special event 1010 Compare mode, generate software interrupt 1001 Compare mode, on match, CCP pin low 1000 Compare mode, on match, CCP pin high 0111 Capture on every sixteenth rising edge 0110 Capture on every fourth rising edge 0101 Capture on every rising edge 0100 Capture on every falling edge 00xx CCP off
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Capture mode is used to time-repeating functions or in determining the length of a PWM pulse. If a PWM pulse is to be timed, then when the start value is loaded, the polarity is reversed to get to the end of the pulse. When timing a PWM pulse, the TMR1 clock must be fast enough to get a meaningful value with a high enough resolution that there will be an accurate representation of the timing. Compare mode changes the state of the CCPx pin of the PIC microcontroller when the contents of TMR1 match the value in the CCPRxM and CCPRxL registers as shown in Fig. 16.7. This mode is used to trigger or control external hardware after a speci c delay.
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CCP Interrupt Request CCP1 Pin
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Prescaler 1:1 1:4 1:16
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CCPR1H
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Edge Detect
TMR1H
TMR1L
CCP1M3:CCP1M0
Block diagram of CCP capture circuitry.
PIC MCU OPTIONAL HARDWARE FEATURES
CCPR1H
CCPR1L
CCP2IF
Comparator
O/P Select
CCP2 Pin
TMR1H
TMR1L
CCP2M3:CCP2M0
Figure 16.7 circuitry.
Block diagram of CCP compare
The most interesting use I ve seen for the compare mode of the CCP is to turn the PIC microcontroller into a watchdog for a complex system. As is shown in Fig. 16.8, the PIC microcontroller controls reset to the system processor. On power-up, the PIC microcontroller holds the processor reset until Vcc has stabilized, and then the TMR1 is reset each time the system writes to the PIC microcontroller. System reset is enabled if after a time-out delay Vcc falls below a speci c level. Using event-driven code, the PIC microcontroller application would look like this:
PowerUpEvent() { TMR1 = 0; TMR1 = on; CCPRx = PowerUpDelay; CCPxCON = 0b000001000; ADCIE = on; } // End PowerUpEvent // TMR1 = Compare / WDT T/O. // PIC microcontroller Power Up
// // // // //
Start TMR1 Put in Watchdog Delay Drive Pin Low and /then High on Compare Match Start ADC Check of Vcc
CompareMatchEvent( ) {
IDE Bus
PIC Micro
ADx PSP
PC System Processor
CCPx
Reset
Figure 16.8 PC watchdog timer using PIC microcontroller with the CCP compare circuitry enabled.
COMPARE/CAPTURE/PWM (CCP) MODULE
CCPxCON = 0; CCPx = 1; } // End CompareMatchEvent
// //
Turn off compare. Reset system
PSPWriteEvent( ) { TMR1 = 0; } // End PSPWriteEvent
// //
PSP Written to Reset WDT Count
ADCIFEvent() { if (ADC < OperatingMinimum) { CCPxCON = 0; CCPx = high; } ADCIF = 0; } // End ADCIFEvent
ADC Finished Vcc check
// //
Turn Off ADC Reset system program
Reset Interrupt Request
PWM OPERATION
Of the three CCP modes, I nd the PWM signal generator to be the most useful. This mode outputs a PWM signal using the TMR2 reset at a speci c value capability. The block diagram of PWM mode is shown in Fig. 16.9. The mode is a combination of the normal execution of TMR2 and capture mode; the standard TMR2 provides the PWM period, whereas the compare control provides the on time speci cation. When the PWM circuit executes, TMR1 counts until its most signi cant 8 bits are equal to the contents of PR2. When TMR2 equals PR2, TMR2 is reset to 0, and the CCPx pin is set high. TMR2 is run in a 10-bit mode (the 4:1 prescaler is enabled before PWM operation). This 10-bit value is then compared with a program value in CCPRxM (along with the two DCxBx bits in CCPxCON), and when they match, the CCPx output pin is reset low. To set up a 65 percent duty cycle in a 20-kHz PWM executing in a PIC microcontroller clocked at 4 MHz, the following steps are taken: First, the CCPRxM and PR2 values are calculated for TMR2; the 4:1 prescaler must be enabled, resulting in a delay of
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