barcode reader application in asp.net Delay = (PR2 + 1) *4 / (frequency/4) PR2 = = = = delay * frequency 1 50msec * 4mHz 1 200 1 199 in Software

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Delay = (PR2 + 1) *4 / (frequency/4) PR2 = = = = delay * frequency 1 50msec * 4mHz 1 200 1 199
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A == B
Figure 16.9 diagram.
CCP PWM generation circuitry block
Then, 65 percent of 200 is 130, which is loaded into CCPRxM. The code for creating the 65 percent 20-kHz PWM is
movlw movwf movlw movwf movlw movwf movlw movwf ; 199 PR2 (1 << TMR2on) + 1 T2CON 130 CCPRxH (1<<DCxB1) + 0x00F CCPxCON
; ; ; ;
Set up TMR2 Operation Start it Running with a 50 msec Period 65% of the Period
Start PWM
PWM is operating
Note that in this code I don t enable interrupts or have to monitor the signal output. In addition, you should notice that I don t use the fractional bits. To use the 2 least signi cant bits, I assume that they are fractional values. For the preceding example, if I wanted to ne-tune the PWM frequency to 65.875 percent, I would recalculate the value as a fraction of the total period. For a period of 200 TMR2 counts with a prescaler of 4, the CCPRxH value becomes 131.75. To operate the PWM, I would load 130 into CCPRxh (subtracting 1 to match TMR2 s zero start) and then the fractional value 0.75 into DCxB1 and DCxB0 bits. I assume that DCxB1 has a value of 0.50 and that DCxB0 has a fractional value of 0.25. Thus, to get a PWM in this case, CCPRxH is loaded with 130, and DCxB1 and DCxB0 are both set. Table 16.5 gives the fractional DCxBX bit values.
SERIAL I/O
TABLE 16.5 FRACTION
CCP DCXBX BIT DEFINITION DCXB1 DCXB0
0.00 0.25 0.50 0.75
00 01 10 11
The least signi cant 2 bits of the PWM obviously are not that important unless a very small PWM on period is used in an application. A good example of this is using the PWM module for an R/C servo. In this case, the PWM period is 20 ms with an on time of 1 to 2 ms. This gives a PWM pulse range of 5 to 10 percent, which makes the DCxB1 and DCxB0 bits important in positioning the servo accurately.
Serial I/O
As with many microcontrollers, the PIC microcontroller has optional built-in serial I/O interfacing hardware. These interfaces, which are available on certain PIC microcontroller part numbers, allow a PIC microcontroller to interface with external memory and enhanced I/O functions (such as ADCs) or communicate with a PC using RS-232. As with other enhanced peripheral features, the serial I/O hardware is available on different PIC microcontrollers, and the hardware may be available differently in different devices.
SYNCHRONOUS SERIAL PORT (SSP) COMMUNICATIONS MODULE
In discussing the synchronous serial port (SSP), I am rst going to discuss its basic operations, followed by the I2C operations in the next section. There are two reasons why I break operation of the SSP into two parts, the rst being that I2C is quite a complex operation that I feel would be best served by a discussion in its own section. The second reason for splitting out the I2C function is the inability of two SSI versions to provide the full range of I2C operations. The SSP and BSSP modules, which are available in many PIC microcontroller part numbers, do not have I2C master mode capabilities. This limits their usefulness in working with I2C (where typically the PIC microcontroller is a master) as compared with PIC microcontrollers equipped with the MSSP (master SSP) module, which does have I2C multimaster capabilities. SPI (its data stream is shown in Fig. 16.10) is an 8-bit synchronous serial protocol that uses 3 data bits to interface with external devices. Data is clocked out, with the most
PIC MCU OPTIONAL HARDWARE FEATURES
Clock
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Line Idle Line Idle
Data
SPI data and clock waveform.
signi cant bit rst, on rising or falling edges of the clock. The clock itself is generated within the PIC microcontroller (master mode), or it is provided by an external device and used by the PIC microcontroller (slave mode) to clock out the data. The clock can be positive, as shown in the gure with a 0 idle or negative (high line idle) with a 1 idle and the clock pulsing to 0 and back again. The data receive latch is generally on the return to idle state transition. The BSSP module is the basic SSP module and provides data pulling on the return to idle clock edge. The original SSP module provides the ability to vary when data is output and read. Controlling the operation of the different SSP modules is the SSPCON register. In describing the operational bits, note that I only describe the SPI-speci c operations in Table 16.6.
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