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TABLE 16.6 BIT
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SSP/BSSP SSPCON REGISTER BIT DEFINITION FUNCTION
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WCOL Write collision, set when new byte written to SSPBUF while transfer is taking place. SSPOV Receive over ow, indicates that the unread byte is SSPBUF overwritten while in SPI slave mode. SSPEN Set to enable the SSP module. CKP Clock polarity select, set to have a high idle. SSPM3 SSPMO SPI mode select 1xxx I2C and reserved modes 011x I2C slave modes 0101 SPI slave mode, clock = SCK pin, _SS not used 0100 SPI slave mode, clock = SCK pin, _SS enabled 0011 SPI master mode, TMR2 clock used 0010 SPI master mode, INSCK/16 0001 SPI master mode, INSCK/4 0000 SPI master mode, INSCK
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SDI _SS
SSPBUF
Reset
Block diagram of SSP SPI module.
The block diagram for the SSP module is shown in Fig. 16.11. In master mode, when a byte is written to SSPBUF, an 8-bit most-signi cant-bit- rst data transfer process is initiated. The status of the transfer can be checked by the SSPSTAT register BF ag; the SSPSTAT register is de ned as shown in Table 16.7. The connection of a PIC microcontroller to an SPI bus is quite straightforward. In Fig. 16.11, two PIC microcontrollers are shown with the SDO and SDI sides connected. To initiate a byte transfer, a byte is written to the SSPBUF of the master. Writing to the SSPBUF of the slave will not initiate a transfer. When SPI mode is enabled, the SDI, SDO, and SCK bits TRIS functions are set appropriately. This is shown in Fig. 16.12. The SSP SPI transfers can be used for single-byte synchronous serial transmits of receivers with serial devices. In Fig. 16.13 I show the circuit to TX a byte to a 74LS374
TABLE 16.7 BIT
SSP/BSSP SSPSTAT BIT DEFINITION FUNCTION
SMP Set to have data sampled after active to idle transition; reset to sample at active-to-idle transition; not available in BSSP. CKE Set to TX data on idle-to-active transition; else TX data on active-to-idle transition; not available in BSSP D/_A Used by I2C. P Used by I2C. S Used by I2C. R/_W Used by I2C. UA Used by I2C. BF Busy ag, reset while SPI operation active.
5 4 3 2 1 0
PIC MCU OPTIONAL HARDWARE FEATURES
SPI master/slave connection.
wired as a serial in, parallel out shift register. In Fig. 16.14. I show a 74LS374 being used with a 74LS244 as a synchronous parallel in, serial out register. Both these operations are initiated by a write to SSPBUF. The SPI data receive operation may be immediately obvious. To latch data into the 74LS374, the I/O pin is driven high; this disables the 74LS374 s drivers, allowing the parallel data to be latched in. When the I/O pin is low, the 74LS244 s drivers are disabled, and the 74LS374 behaves like a shift register.
PIC Micro
374
Bit 7
3Q SDO SCK _OE 1Q 2D 2Q 1D
Bit 1
Bit 0
Figure 16.13 Wiring connection to pass SPI data from the PIC microcontroller to a serial-to-parallel converter.
SERIAL I/O
PIC Micro
374
7Q 6D
244
Bit 7
SDI SCK
2Q 1D 1Q _OE _OE
Bit 1 Bit 0
Figure 16.14 Wiring to bring data from a parallel-to-serial converter into a PIC microcontroller.
To show this, here is some code to read the input state of Fig. 16.14. Note that I disable the SSPEN bit when a transfer is not taking place to allow the I/O pin and SCK to strobe in the data.
bsf IOPin ; Want to Latch Data into the 374 bcf SCK bsf STATUS, RPO bcf IOpin bcf SCK bcf STATUS, RP0 bsf SCK ; Latch the Data into the 374 bcf SCK bcf IOpin ; Disable 244 output, Enable 374 movlw (I << SMP) + (I << CKE) movwf SSPSTAT ; Set up the SSP Shift In movlw (I << SSPEN) + (I << CKP) +0x000 movwf SSPCON movf TXData, f ; Load the Byte to Send movwf SSPBUF ; Start Data Transfer btfss SSPTAT, BF goto $ - 1 ; Wait for Data Receive to Complete ; Data Ready in SSPBUF when Execution ; Here bcf SSPCON, SSPEN ; Turn off SSP
When using the SSP, the data rate either can be selected as a multiple of the executing clock or use the TMR2 over ow output. The actual timing depends on the hardware the PIC microcontroller SSP master is communicating with.
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